RG82845 S L5YQ Intel, RG82845 S L5YQ Datasheet - Page 90

• Manufacturer Part Number: RG82845 S L5YQ
• Manufacturer: Intel

Specifications of RG82845 S L5YQ

• Lead Free Status / RoHS Status: Not Compliant

Register Description
3.6.17
3.6.18
90
Note: Memory range covered by MBASE1 and MLIMIT1 registers are used to map non-prefetchable
MBASE1—Memory Base Address Register (Device 1)
Address Offset:
Default Value:
Access:
Size:
This register controls the host to AGP non-prefetchable memory accesses routing based on the
following formula:
The upper 12 bits of the register are read/write and correspond to the upper 12 address bits
A[31:20] of the 32-bit address. The bottom 4 bits of this register are read-only and return 0s when
read. The configuration software must initialize this register. For the purpose of address decode,
address bits A[19:0] are assumed to be 0. Thus, the bottom of the defined memory address range
will be aligned to a 1 MB boundary.
MLIMIT1—Memory Limit Address Register (Device 1)
Address Offset:
Default Value:
Access:
Size:
This register controls the host to AGP non-prefetchable memory accesses routing based on the
following formula:
The upper 12 bits of the register are read/write and correspond to the upper 12 address bits
A[31:20] of the 32-bit address. The bottom 4 bits of this register are read-only and return 0s when
read. The configuration software must initialize this register. For the purpose of address decode,
address bits A[19:0] are assumed to be FFFFFh. Thus, the top of the defined memory address
range will be at the top of a 1 MB aligned memory block.
AGP address ranges (typically, where control/status memory-mapped I/O data structures of the
graphics controller will reside) and PMBASE 1and PMLIMIT1 Registers are used to map
prefetchable address ranges (typically, graphics local memory). This segregation allows
application of USWC space attributes to be performed in a true plug-and-play manner to the
prefetchable address range for improved host-AGP memory access performance.
MEMORY_BASE1
MEMORY_BASE1
15:4
Bit
3:0
15:4
Bit
3:0
Memory Address Limit 1(MEM_LIMIT1). Corresponds to A[31:20] of the memory address.
Default=0
Reserved.
Memory Address Base 1 (MEM_BASE1). Corresponds to A[31:20] of the memory address.
Reserved.
address
address
MEMORY_LIMIT1
MEMORY_LIMIT1
20–21h
FFF0h
R/W
16 bits
22–23h
0000h
R/W
16 bits
Description
Description
Intel
®
82845 MCH for SDR Datasheet
R