RG82845 S L5YQ Intel, RG82845 S L5YQ Datasheet - Page 83

• Manufacturer Part Number: RG82845 S L5YQ
• Manufacturer: Intel

Specifications of RG82845 S L5YQ

• Lead Free Status / RoHS Status: Not Compliant

3.6.4
Intel
®
82845 MCH for SDR Datasheet
R
PCISTS1—PCI-PCI Status Register (Device 1)
Address Offset:
Default Value:
Access:
Size:
PCISTS1 is a 16-bit status register that reports the occurrence of error conditions associated with
primary side of the “virtual” PCI-PCI bridge embedded n the MCH. Since this device does not
physically reside on PCI_A, it reports the optimum operating conditions so that it does not restrict
the capability of PCI_A.
10:9
Bit
4:0
15
14
13
12
11
8
7
6
5
possible decode.
capable.
Detected Parity Error (DPE1)—RO. Not Implemented; Hardwired to 0.
Signaled System Error (SSE1)—R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = MCH device 1 generated an SERR message over the hub interface for any enabled Device
Received Master Abort Status (RMAS1)—RO. Not Implemented; Hardwired to 0.
Received Target Abort Status (RTAS1)—RO. Not Implemented; Hardwired to 0.
Signaled Target Abort Status (STAS1)—RO. Not Implemented; Hardwired to 0.
DEVSEL# Timing (DEVT1)—RO. Hardwired to 00b. Indicate that the device 1 uses the fastest
Data Parity Detected (DPD1). Not Implemented; Hardwired to 0.
Fast Back-to-Back (FB2B1)—RO. Hardwired to 1. The AGP port always supports fast back to
back transactions.
Reserved.
66 MHz Capability (CAP66)—RO. Hardwired to 1. Indicates that the AGP port is 66 MHz
Reserved.
1 error condition. Device 1 error conditions are enabled in the ERRCMD, PCICMD1 and
BCTRL1 registers. Device 1 error flags are read/reset from the ERRSTS and SSTS1
register.
06–07h
00A0h
RO, R/WC
16 bits
Descriptions
Register Description
83