RG82845 S L5YQ Intel, RG82845 S L5YQ Datasheet - Page 80

• Manufacturer Part Number: RG82845 S L5YQ
• Manufacturer: Intel

Specifications of RG82845 S L5YQ

• Lead Free Status / RoHS Status: Not Compliant

Register Description
3.6
80
Table 10. Intel
Bridge Registers (Device 1)
Table 10. provides the register address map for Device 0 PCI configuration space. An “s” in the
Default Value column indicates that a strap determines the power-up default value for that bit.
Address
1E–1Fh
0F–17h
28–3Dh
41–4Fh
02–03h
04–05h
06–07h
20–21h
22–23h
24–25h
26–27h
50–57h
00-01h
Offset
®
0Ah
0Bh
0Ch
0Dh
0Eh
1Ah
1Bh
1Ch
1Dh
3Eh
18h
19h
3Fh
40h
08
09
MCH Configuration Space (Device 1)
ERRCMD1
SUBUSN1
PMBASE1
PCICMD1
PMLIMIT1
PCISTS1
IOBASE1
IOLIMIT1
MBASE1
PBUSN1
SBUSN1
MLIMIT1
BCTRL1
Symbol
SUBC1
SMLT1
SSTS1
DWTC
BCC1
HDR1
MLT1
VID1
DID1
RID1
—
—
—
—
—
—
Vendor Identification
Device Identification
PCI Command
PCI Status
Revision Identification
Reserved
Sub-Class Code
Base Class Code
Reserved
Master Latency Timer
Header Type
Reserved
Primary Bus Number
Secondary Bus Number
Subordinate Bus Number
Secondary Bus Master Latency Timer
I/O Base Address
I/O Limit Address
Secondary Status
Memory Base Address
Memory Limit Address
Prefetchable Memory Base Address
Prefetchable Memory Limit Address
Reserved
Bridge Control
Reserved
Error Command
Reserved
DRAM Write Thermal Management Control
Name
Intel
®
82845 MCH for SDR Datasheet
8086h
1A31h
0000h
00A0h
03h, 04h
—
04h
06h
—
00h
01h
—
00h
00h
00h
00h
F0h
00h
02A0h
FFF0h
0000h
FFF0h
0000h
—
00h
—
00h
—
0000000
0h
Default
RO
RO, R/W
R/W
R/W
R/W
R/W
RO, R/WC
R/W
R/W
R/W
RO, R/W
R/W
RO
RO, R/WC
RO
—
RO
RO
—
RO
—
RO
R/W
R/W
R/W
—
—
—
R/W/L
Access
R