RG82845 S L5YQ Intel, RG82845 S L5YQ Datasheet - Page 95

• Manufacturer Part Number: RG82845 S L5YQ
• Manufacturer: Intel

Specifications of RG82845 S L5YQ

• Lead Free Status / RoHS Status: Not Compliant

3.6.24
Intel
®
82845 MCH for SDR Datasheet
R
DRTC—DRAM Read Thermal Management Control Register
(Device 1)
Address Offset:
Default Value:
Access:
Size:
63:41
40:28
27:22
21:15
14:3
Bit
2:1
0
Reserved.
Global Read Hexword Threshold (GRHT). The thirteen-bit value held in this field is multiplied by
2
Sampling Window to cause the thermal management mechanism to be invoked.
Read Thermal Management Time (RTMT). This value provides a multiplier between 0 and 63
that specifies how long counter-based read thermal management remains in effect as a number
of Global DRAM Read Sampling Windows. For example, if GDRSW is programmed to
1000_0000b and RTT is set to 01_0000b, then read thermal management will be performed for
8192*10
Read Thermal Management Monitoring Window (RTMMW). The value in this register is
padded with four 0s to specify a window of 0–2047 host clocks with 16-clock granularity. While
the thermal management mechanism is invoked, system memory reads are monitored during this
window. If the number of hexwords read during the window reaches the Read Thermal
Management Hexword Maximum (bits 14:3), then read requests are blocked for the remainder of
the window.
Read Thermal Management Hexword Maximum (RTMHM). This field defines the maximum
number of hexwords between 0–4095 that are permitted to be read from system memory within
one Read Thermal Management Monitoring Window.
Read Thermal Management Mode (RTMMode).
00 = Thermal management via counters and Hardware Thermal Management_on signal
01 = Hardware Thermal Management_on signal mechanism is enabled. In this mode, as long as
10 = Counter mechanism controlled through GDRSW and GRHT is enabled. When the threshold
11 = Reserved.
START Read Thermal Management (SRTM). Software writes to this bit to start and stop read
thermal management.
0 = Read thermal management stops and the counters associated with RTMW and RTHM are
1 = Read thermal management begins based on the settings in RTMW and RTHM, and remains
15
to arrive at the number of hexwords that must be written within the Global DRAM Read
reset.
to be in effect until this bit is reset to 0.
mechanisms disabled.
the Thermal Management_on signal is asserted, read thermal management is in effect
based on the settings in RTMW and RTHM. When the Thermal Management_on signal is
deasserted, read thermal management stops and the counters associated with the RTMW
and RTHM are reset. When the hardware Thermal Management_on signal mechanism is
not enabled, the Thermal Management_on signal has no effects.
set in GDRSW and GRHT is reached, thermal management start/stop cycles occur based
on the settings in RTT, RTMW and RTHM.
5
host clocks (@ 100 MHz) seconds once invoked (128 * 4*10
58–5Fh
0000_0000_0000_0000h
R/W/L
64 bits
Descriptions
5
host clocks * 16).
Register Description
95