RG82845 S L5YQ Intel, RG82845 S L5YQ Datasheet - Page 39
RG82845 S L5YQ
Manufacturer Part Number
RG82845 S L5YQ
Description
Manufacturer
Intel
Datasheet
1.RG82845_S_L5YQ.pdf
(148 pages)
Specifications of RG82845 S L5YQ
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3.4.3
Intel
®
82845 MCH for SDR Datasheet
R
CKESTR—Strength Control Register (SCKE Signal Group)
Memory Address Offset:
Default Value:
Access:
Size:
This register controls the drive strength of the I/O buffers for the CKE signal group. This group
has two possible loadings depending on the width of SDRAM devices used in each row of memory
(x8 or x16). The proper strength can be independently programmed for each configuration. The
actual strength used for each signal is determined by the DRAMWIDTH Register (offset 2Ch).
6:4
2:0
Bit
7
3
Reserved.
SCKE x16 Strength Control. This field selects the signal drive strength.
000 = 0.75 X (default)
001 = 1.00 X
010 = 1.25 X
011 = 1.50 X
100 = 2.00 X
101 = 2.50 X
110 = 3.00 X
111 = 4.00 X
Reserved.
SCKE x8 Strength Control. This field selects the signal drive strength.
000 = 0.75 X (default)
001 = 1.00 X
010 = 1.25 X
011 = 1.50 X
100 = 2.00 X
101 = 2.50 X
110 = 3.00 X
111 = 4.00 X
31h
00h
R/W
8 bits
Descriptions
Register Description
39
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