RG82845 S L5YQ Intel, RG82845 S L5YQ Datasheet - Page 113

• Manufacturer Part Number: RG82845 S L5YQ
• Manufacturer: Intel

Specifications of RG82845 S L5YQ

• Lead Free Status / RoHS Status: Not Compliant

Intel
Table 15. AGP Commands Supported by the Intel
®
82845 MCH for SDR Datasheet
R
NOTES:
As a target of an AGP cycle, the MCH supports all the transactions targeting system memory
(summarized in Table 15). The MCH supports both normal and high-priority read and write
requests. The MCH does not support AGP cycles to the hub interface. PIPE# and SBA cycles do
not require coherency management and all AGP initiator accesses to system memory, using AGP
PIPE# or SBA protocol, are treated as non-snoopable cycles. These accesses are directed to the
AGP aperture in system memory that is programmed as either uncacheable (UC) memory or write
combining (WC) in the processor’s MTRRs.
Read
Hi-Priority Read
Reserved
Reserved
Write
Hi-Priority Write
Reserved
Reserved
Long Read
Hi-Priority Long
Read
Flush
Reserved
Fence
Reserved
Reserved
Reserved
1. N/A refers to a function that is not applicable
Command
AGP
C/BE[3:0]#
Encoding
0000
0000
0001
0000
0010
0011
0100
0100
0101
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
System memory
Hub interface
System memory
The Hub interface
N/A
N/A
System memory
Hub interface
System memory
Hub interface
N/A
N/A
System memory
Hub interface
System memory
Hub interface
MCH
N/A
MCH
N/A
N/A
N/A
Cycle Destination
®
MCH When Acting as an AGP Target
MCH Host Bridge
Low-priority read
Complete with random data
High-priority read
Complete with random data
No response
No response
Low-priority write
Cycle goes to DRAM with byte
enables inactive
High-priority write
Cycle goes to DRAM with byte
enables inactive; does not go to
the hub interface
No response
No response
Low-priority read
Complete locally with random data;
does not go to the hub interface
High-priority read
Complete with random data
Complete with QW of random data
No response
No response; Flag inserted in
MCH request queue
No response
No response
No response
Response as PCIx Target
Functional Description
113