PEF20550HV2.1XT Infineon Technologies, PEF20550HV2.1XT Datasheet - Page 102

• Manufacturer Part Number: PEF20550HV2.1XT
• Manufacturer: Infineon Technologies

Specifications of PEF20550HV2.1XT

• Lead Free Status / Rohs Status: Compliant

channel. There are two different interrupt indications concerned with the reception of
data:
– A RPF (Receive Pool Full) interrupt indicates that a 32-byte block of data can be read
– A RME (Receive Message End) interrupt indicates that the reception of one message
The CPU must handle the RPF-interrupt before additional 32 bytes are received via the
serial interface, as failure to do so causes a RDO (Receive Data Overflow).
Status information about the received frame is appended to the frame in the RFIFO. This
status information follows the format of the RSTA-register, unless using the SACCO-A
in clock mode 3. The CPU can read the length of the received message (including the
appended Receive Status byte) from the RBCH- and RBCL-registers.
After the received data has been read from the RFIFO, this must be explicitly
acknowledged by the CPU issuing a RMC- (Receive Message Complete)
command!
The following figure gives an example of an interrupt controlled reception sequence,
supposing that a long frame (66 bytes) followed by a short frame (6 bytes) are received.
Figure 52
Interrupt Driven Reception Example
3.6.3
In receive direction 2
Semiconductor Group
from the RFIFO with the received message not yet complete.
is completed, i.e. either
– one message with less than 32 bytes, or the
– last part of a message with more than 32 bytes
is stored in the CPU accessible part of the RFIFO.
Serial
Interface
SACCO
CPU
Interface
Data Reception in Interrupt Mode
Receive 66 Bytes
32
RPF
32 Bytes
RFIFO
32
32-byte FIFO-buffers (receive pools) are also provided for each
RMC
RPF
2
32 Bytes
RFIFO
Receive
6 Bytes
6
RMC
RME
102
Count
Byte
3 Bytes
RFIFO
RMC
RME
Operational Description
Count
Byte
7 Bytes
RFIFO
PEB 20550
PEF 20550
RMC
ITD05849
01.96