PEF20550HV2.1XT Infineon Technologies, PEF20550HV2.1XT Datasheet - Page 345

• Manufacturer Part Number: PEF20550HV2.1XT
• Manufacturer: Infineon Technologies

Specifications of PEF20550HV2.1XT

• Lead Free Status / Rohs Status: Compliant

PEB 20550
PEF 20550
Application Hints
be set. If not required, the D-channel can also be sent transparently. If the QUAT-S is
used together with the IDEC as layer-2 controller, the IDEC must be informed about the
availability of the D-channel at the T-interface. The QUAT-S provides an enable signal
at pin DRDY that carries this information during the D-channel timeslot. This signal can
be connected to the collision data input (CDR) of the IDEC to enable or disable HDLC
transmission. The IDEC must then be programmed to the ‘slave mode’ in order to
evaluate the CDR pin.
Figure 118 illustrates a complete PBX trunk card, where the ELIC controls up to
8 QUAT-S devices connected to up to 4 IOM-2 ports. On each IOM-2 port 2 IDECs take
care of the D-channel processing. The CDR input lines of the IDECs are connected with
the DRDY output pins of the QUAT-S. This is to stop the HDLC controllers in case of a
D-channel collision on the T-bus. The QUAT-S devices must be programmed via the
monitor channel to deliver appropriate Stop/Go information at pin DRDY. The 1536 kHz
reference clock outputs (pin CLK1) of the QUAT-Ss are fed via a multiplexer to the PBX
clock generator. The P controls the multiplexer as required by the state of the lines.
Semiconductor Group
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