PEF20550HV2.1XT Infineon Technologies, PEF20550HV2.1XT Datasheet - Page 396

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PEF20550HV2.1XT

Manufacturer Part Number
PEF20550HV2.1XT
Description
Manufacturer
Infineon Technologies
Datasheet

Specifications of PEF20550HV2.1XT

Lead Free Status / Rohs Status
Compliant
9
9.1
• In demultiplexed address mode the ELIC registers can (in comparison to the EPIC-1)
• The demultiplexed addresses can also be used in multiplexed mode (see register
• The ELIC-EPIC has 4 PCM modes. PCM mode 3 is similar to PCM mode 1 unlike in
• The error in the double last look logic of the EPIC-1 up to Version A3 (6 bit C/I-channel
• In preprocessed applications the combination of MACR:CMC3..0 = 1010 (for the even
• In a double clock rate configuration (clock frequency is twice the data rate), the ELIC
• The ELIC is able to generate a 2 Mbit/s (PCM and CFI) datastream out of a 2 MHz
9.2
The following pages contain some working sheets to facilitate the programming of the
EPIC-1. For several tasks (i.e. initialization, time slot switching, ...) the corresponding
registers are summarized in a way the programmer gets a quick overview on the
registers he has to use.
Semiconductor Group
additionally be addressed by A4..A0 (see register OMDR:RBS).
If A4 is connected to ground, the registers are addressed by A3..A0 and RBS. This is
compatible to the EPIC-1.
EMOD:DMXAD).
PCM mode 1 the pins TXD1, TXD3 are not tristated, but drive the inverted values of
TXD0, TXD2.
change in time slot 1 and 3 will not be recognized; see EPIC errata sheet 02.95) was
corrected in ELIC-EPIC.
CMC address field) is used in downstream direction for the D-channel handling of
SACCO_A with the arbiter.
PCM input and output data can be shifted additionally by one PDC clock (see register
bits PCSR:DRCS and PCSR:ADSRO). If these two bits are not set, the ELIC-EPIC is
compatible to the EPIC-1.
This feature guarantees the capability to adapt to a PCM data stream also in double
clock rate mode (unlike the EPIC-1 up to Version A3), when the negative PDC edge
is used to synchronize PFS.
PCM clock also in CFI mode 0. See register EMOD:ECMD2.
Appendix
Differences between EPIC
Working Sheets
®
-1 (PEB 2055) and the ELIC
396
®
-EPIC
®
PEB 20550
PEF 20550
Appendix
01.96

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