PEF20550HV2.1XT Infineon Technologies, PEF20550HV2.1XT Datasheet - Page 125

• Manufacturer Part Number: PEF20550HV2.1XT
• Manufacturer: Infineon Technologies

Specifications of PEF20550HV2.1XT

• Lead Free Status / Rohs Status: Compliant

IDA
IEP
EXB
ICB
EXA
ICA
Each interrupt source/group can be selectively masked by setting the respective bit in
the MASK-register (bit position corresponding to the ISTA-register). A masked IDA-
interrupt is not indicated when reading ISTA. Instead it remains internally stored and will
be indicated after the respective MASK-bit is reset. The watchdog timer interrupts is not
maskable.
Even with a set MASK-bit EPIC-1 and SACCO-interrupts are indicated but no interrupt
signal is generated.
When writing the MASK-register while an interrupt is indicated, INT is temporarily set into
the inactive state.
4.2.2
Access in demultiplexed P-interface mode:
Access in multiplexed P-interface mode:
Reset value: 00
Semiconductor Group
bit 7
0
Mask Register (MASK)
enables(0)/disables(1) the D-Channel Arbiter interrupt
enables(0)/disables(1) the EPIC-1 Interrupts
enables(0)/disables(1) the SACCO-B Extended interrupts
enables(0)/disables(1) the SACCO-B Interrupts
enables(0)/disables(1) the SACCO-A Extended interrupts
enables(0)/disables(1) the SACCO-A Interrupts
IDA
H
(all interrupts enabled)
IEP
EXB
125
ICB
write
write
Detailed Register Description
EXA
address: 82
address: 41
ICA
PEB 20550
PEF 20550
bit 0
H
H
0
01.96