PEF20550HV2.1XT Infineon Technologies, PEF20550HV2.1XT Datasheet - Page 34

• Manufacturer Part Number: PEF20550HV2.1XT
• Manufacturer: Infineon Technologies

Specifications of PEF20550HV2.1XT

• Lead Free Status / Rohs Status: Compliant

1.6.1.6 Mixed D-Channel Processing, Signaling Decentralized,
Another possibility is a mixed architecture with centralized packet data and decentralized
signaling handling. This is a very flexible architecture which reduces the dynamic load of
central processing units by evaluating the signaling information on the line card, but does
not require resources for packet data handling. Any increase of packet data traffic does
not necessitate a change in the line card architecture, the central packet handling unit
can be expanded.
Also in this application IDECs are employed to handle the data on the D-channel. The
IDECs separate signaling information from data packets. The signaling messages are
transferred to the P, which in turn hands them over to the group controller using the
SACCO. The packet data is processed differently. Together with the collision resolution
information it is transferred to one IOM-2 interface of the ELIC. The EPIC-1 switches the
channels to the PCM-highway, optionally combining four D-channels to one 64-kbit/s
channel. In this configuration one IOM-2 interface is occupied by IDECs, reducing the
total switching capability of the EPIC-1 to 24 ISDN-subscribers.
Figure 15
Line Card Architecture for Mixed D-Channel Processing
Semiconductor Group
Sig.
Data
IOM -2 Interface
Packet Data Centralized
R
IDEC
p-Data
µP
R
Signaling
IDEC
P+Coll
R
P
SACCO CH-A
SACCO CH-B
ARBITER
B, P, C
EPIC
ELIC
R
R
34
ITS05816
B
S
B
Example Frame Structure
PCM
Highway
Signaling
Highway
...
B
Packet
Data
P
PEB 20550
PEF 20550
B
Overview
Collision
Data
C
01.96
B