PEF20550HV2.1XT Infineon Technologies, PEF20550HV2.1XT Datasheet - Page 180

• Manufacturer Part Number: PEF20550HV2.1XT
• Manufacturer: Infineon Technologies

Specifications of PEF20550HV2.1XT

• Lead Free Status / Rohs Status: Compliant

4.7.17 Receive Address Byte Low Register 2 (RAL2)
Access in demultiplexed P-interface mode:
Access in multiplexed P-interface mode:
Reset value: xx
RAL27..20
Note: Normally used for broadcast address.
4.7.18 Receive Address Byte High Register 1 (RAH1)
Access in demultiplexed P-interface mode:
Access in multiplexed P-interface mode:
Reset value: xx
RAL17..12
Note: When a 1-byte address field is used in non-auto or auto-mode, RAH1 must be set
Semiconductor Group
bit 7
bit 7
RAH17
RAL27
to 00
H
.
RAH16
RAL26
Receive Address byte Low register 1.
Receiver Address byte High register 1.
H
H
Auto-mode, non-auto mode (address recognition):
compare value 2, address recognition (low byte in case of 2-byte
address field).
Auto-mode, non-auto mode transparent mode 1, (2-byte address field).
Compare value 1, high byte address recognition.
RAH15
RAL25
RAH14
RAL24
180
RAH13
RAL23
write
write
write
write
address: (Ch-A/Ch-B): 29
address: (Ch-A/Ch-B): 52
address: (Ch-A/Ch-B): 26
address: (Ch-A/Ch-B): 4C
Detailed Register Description
RAH12
RAL22
RAL21
0
PEB 20550
PEF 20550
bit 0
bit 0
RAL20
H
H
H
H
/69
/D2
/66
0
/CC
01.96
H
H
H
H