PEF20550HV2.1XT Infineon Technologies, PEF20550HV2.1XT Datasheet - Page 301

• Manufacturer Part Number: PEF20550HV2.1XT
• Manufacturer: Infineon Technologies

Specifications of PEF20550HV2.1XT

• Lead Free Status / Rohs Status: Compliant

ISTA_E
will still be set to logical 1.
5.5.2.2 Access to Downstream C/I and SIG Channels
If two consecutive downstream CFI timeslots, starting with an even timeslot number, are
programmed as MF and CS channels, the P can write a 4, 6 or 8 bit wide C/I or SIG
value to the even addressed downstream CM data field. This value will then be
transmitted repeatedly in the odd CFI timeslot until a new value is loaded.
This value, first written into MADR, can be transferred to the CM data field using the
memory operation codes MACR:MOC = 111X or MACR:MOC = 1001 (refer to
chapter 5.3.3.3).
The code MACR:MOC = 111X applies if the code field has not yet been initialized with
a CS channel code. Writing to MACR with MACR:RWS = 0 will then copy the CS channel
code written to MACR:CMC3 … CMC0 to the CM code field and the value written to
MADR to the CM data field. The CM address (CFI timeslot) is specified by MAAR
according to figure 84.
The code MACR:MOC = 1001 applies if the code field has already been properly
initialized with a CS channel code. In this case only the MADR content will be copied to
the CM data field addressed by MAAR.
Interrupt Status Register EPIC
The ISTA_E register should be read after an interrupt in order to determine the interrupt
source.
In connection with the signaling handler one maskable (MASK_E) interrupt bit is
provided by the ELIC in the ISTA_E register:
SFI:
Note that the MASK_E:SFI bit only disables the interrupt pin (INT); the ISTA_E:SFI bit
Semiconductor Group
bit 7
TIN
Signaling FIFO Interrupt; This bit is set to logical 1 if there is at least
one valid entry in the CIFIFO indicating a change in a C/I or SIG
channel. Reading ISTA_E does not clear the SFI bit. Instead SFI is
cleared (logical 0) if the CIFIFO is empty which can be accomplished
by reading all valid entries of the CIFIFO or by resetting the CIFIFO
by setting CMDR:CFR to 1.
SFI
MFFI
®
read
MAC
301
PFI
reset value:
PIM
Application Hints
SIN
00
PEB 20550
PEF 20550
H
bit 0
SOV
01.96