PEF20550HV2.1XT Infineon Technologies, PEF20550HV2.1XT Datasheet - Page 334

• Manufacturer Part Number: PEF20550HV2.1XT
• Manufacturer: Infineon Technologies

Specifications of PEF20550HV2.1XT

• Lead Free Status / Rohs Status: Compliant

PICM:
The following register bits are used in conjunction with the PCM input comparison
function:
PCM Mode Register
PMOD:
AIC1 … 0:
Interrupt Status Register EPIC
ISTA_E:
The ISTA_E register should be read after an interrupt in order to determine the interrupt
source. In connection with the PCM comparison function one maskable (MASK_E)
interrupt bit is provided by the ELIC:
PIM:
PCM Input Comparison Mismatch
The contents of the PICM register is only valid after an ISTA_E:PIM interrupt!
Semiconductor Group
bit 7
bit 7
bit 7
PMD1
IPN
TIN
Alternative Input Comparison 1 and 0.
AIC0 set to logical 1 enables the comparison function between RxD0
and RxD1.
AIC1 set to logical 1 enables the comparison function between RxD2
and RxD3.
AIC1, AIC0 set to logical 0 disables the respective comparison
function.
In PCM mode 2, AIC0 must be set to logical 0.
PCM Input Mismatch; this bit is set to logical 1 immediately after the
comparison logic has detected a mismatch between a pair of PCM
input lines. The exact reason for the interrupt can be determined by
reading the PICM register. Reading ISTA_E clears the PIM bit. A new
PIM interrupt can only be generated after the PICM register has been
read.
PMD0
TSN6
SFI
TSN5
MFFI
PCR
®
TSN4
MAC
PSM
334
read/write reset value:
read
read
TSN3
AIS1
PFI
reset value:
reset value:
TSN2
AIS0
PIM
Application Hints
TSN1
AIC1
SIN
00
00
undefined
PEB 20550
PEF 20550
H
H
bit 0
bit 0
bit 0
TSN0
AIC0
SOV
01.96