PEF20550HV2.1XT Infineon Technologies, PEF20550HV2.1XT Datasheet - Page 178

• Manufacturer Part Number: PEF20550HV2.1XT
• Manufacturer: Infineon Technologies

Specifications of PEF20550HV2.1XT

• Lead Free Status / Rohs Status: Compliant

4.7.13 Receive HDLC-Control Register (RHCR)
Access in demultiplexed P-interface mode:
Access in multiplexed P-interface mode:
Reset value: xx
RHCR7..0 Receive HDLC-Control Register.
Note: The value in RHCR corresponds to the last received frame.
4.7.14 Transmit Address Byte 1 (XAD1)
Access in demultiplexed P-interface mode:
Access in multiplexed P-interface mode:
Reset value: xx
XAD17..10
Semiconductor Group
bit 7
bit 7
RHCR7
XAD17
The contents of the RHCR depends on the selected operating mode.
Note: RR-frames and I-frames with the first byte = AxH (PBCcommand
RHCR6
XAD16
Auto-mode (1- or 2-byte address field):
I-frame
else
Non-auto mode (1-byte address field): 2nd byte after flag
Non-auto mode (2-byte address field): 3rd byte after flag
Transparent mode 1:
Transparent mode 0:
Transmit Address byte 1.
The value stored in XAD1 is included automatically as the address byte
(high address byte in case of 2-byte address field) of all frames transmitted
in auto mode.
Using a 2 byte address field, XAD11 and XAD10 have to be set to ’0’.
H
H
"transmit prepared data") are handled automatically and are not
transferred to the CPU (no interrupt is issued).
RHCR5
XAD15
RHCR4
XAD14
178
RHCR3
XAD13
read
read
write
write
compressed control field
(bit 7-4: bit 7-4 of PBC-command,
bit 3-0: bit 3-0 of HDLC-control field)
HDLC-control field
address: (Ch-A/Ch-B): 29
address: (Ch-A/Ch-B): 52
3nd byte after flag
2nd byte after flag
address: (Ch-A/Ch-B): 24
address: (Ch-A/Ch-B): 48
Detailed Register Description
RHCR2
XAD12
RHCR1
XAD11
PEB 20550
PEF 20550
bit 0
bit 0
RHCR0
XAD10
H
H
H
H
/69
/D2
/64
/C8
01.96
H
H
H
H