PEF20550HV2.1XT Infineon Technologies, PEF20550HV2.1XT Datasheet - Page 77

• Manufacturer Part Number: PEF20550HV2.1XT
• Manufacturer: Infineon Technologies

Specifications of PEF20550HV2.1XT

• Lead Free Status / Rohs Status: Compliant

Together TSN and CS provide 9 bits to determine the location of the time slot for the
HDLC channel.
One of up to 64 time slots can be programmed independently for receive and transmit
direction via the registers TSAR and TSAX.
According to the value programmed via those bits, the receive/transmit window (time
slot) starts with a delay of 1 (minimum delay) up to 512 clock periods following the frame
synchronization signal and is active during the number of clock periods programmed via
RCCR, XCCR (number of bits to be received/transmitted within a time slot) as shown in
figure 42.
Figure 42
Location of Time Slots
Note: In extended transparent mode the width of the time slot has to be n
Semiconductor Group
TSAR
TSAX
HDC
HFS
Time-Slot Number
TSN (6 Bits)
(1...512 Clocks)
1+TSNx8+CS
TSNR
TSNX
Delay
9 Bits
77
RCS 2
XCS 2
Clock Shift
CS (3 Bits)
(1...256 Clocks)
RCS 1
XCS 1 XCS 0
RCCR, XCCR
Time-Slot
Width
RCS 0
Functional Description
CCR 2
ITD05839
PEB 20550
PEF 20550
8 bit.
01.96