PEF20550HV2.1XT Infineon Technologies, PEF20550HV2.1XT Datasheet - Page 239

• Manufacturer Part Number: PEF20550HV2.1XT
• Manufacturer: Infineon Technologies

Specifications of PEF20550HV2.1XT

• Lead Free Status / Rohs Status: Compliant

The use of the data field depends on the function defined by the code field. If a CFI
timeslot is defined as a switched channel, the data field is interpreted as a pointer to the
data memory and defines therefore to which PCM timeslot the connection shall be made.
For preprocessed channels, the data field serves as a buffer for the command/indication
or signaling value. If a P channel is programmed, the data field content is directly
exchanged with the CFI timeslot.
The data memory refers to the PCM interface such that for each upstream timeslot
there is a 4 bit code field and an 8 bit data field location, whereas for each downstream
timeslot there is only an 8 bit data field location.
The data field locations buffer the PCM data transmitted and received over the PCM
interface. The code field (tristate field) defines whether the upstream data field contents
should be transmitted in the associated PCM timeslot or whether the timeslot should be
switched to high impedance.
5.3
5.3.1
The ELIC memory is composed of the Control Memory (CM) and the Data Memory
(DM). Their structure is shown in figure 83.
The control memory refers to the Configurable Interface (CFI) such that for each CFI
timeslot and for each direction (upstream and downstream) there is a 4 bit code field and
an 8 bit data field location.
The code field defines the function of the corresponding CFI timeslot. A timeslot, may for
example, be transparently switched through to the PCM interface (switched channel) or
it may serve as monitor, feature control, command/indication or signaling channel in an
IOM or SLD application (preprocessed channel) or it may be directly switched to the P
interface ( P channel).
Semiconductor Group
Data and Control Memories
Memory Structure
239
Application Hints
PEB 20550
PEF 20550
01.96