PEF20550HV2.1XT Infineon Technologies, PEF20550HV2.1XT Datasheet - Page 181

• Manufacturer Part Number: PEF20550HV2.1XT
• Manufacturer: Infineon Technologies

Specifications of PEF20550HV2.1XT

• Lead Free Status / Rohs Status: Compliant

RBC7..0
4.7.19 Receive Address Byte High Register 2 (RAH2)
Access in demultiplexed P-interface mode:
Access in multiplexed P-interface mode:
Reset value: xx
RAL27..22
Note: When a 1-byte address field is used in non-auto or auto-mode, RAH2 must be set
4.7.20 Receive Byte Count Low (RBCL)
Access in demultiplexed P-interface mode:
Access in multiplexed P-interface mode:
Reset value: 00
Semiconductor Group
bit 7
bit 7
RAH27
RBC7
to 00
H
Receive Byte Count.
Together with RBCH (bits RBC11 - RBC8), the length of the actual received
frame (0…4095 bytes) can be determined. These registers must be read by
the CPU following a RME interrupt.
.
RAH26
RBC6
Receiver Address byte High register 2.
H
H
Auto-mode, non-auto mode transparent mode 1, (2-byte address field).
Compare value 2, high byte address recognition.
RAH25
RBC5
RAH24
RBC4
181
RAH23
RBC3
write
write
read
read
address: (Ch-A/Ch-B): 27
address: (Ch-A/Ch-B): 4E
address: (Ch-A/Ch-B): 25
address: (Ch-A/Ch-B): 4A
Detailed Register Description
RAH22
RBC2
RBC1
0
PEB 20550
PEF 20550
bit 0
bit 0
RBC0
H
H
H
H
/67
/65
0
/CE
/CA
01.96
H
H
H
H