PEF20550HV2.1XT Infineon Technologies, PEF20550HV2.1XT Datasheet - Page 17

• Manufacturer Part Number: PEF20550HV2.1XT
• Manufacturer: Infineon Technologies

Specifications of PEF20550HV2.1XT

• Lead Free Status / Rohs Status: Compliant

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Pin Definitions and Functions (cont’d)
Pin No.
77
78
79
80
Semiconductor Group
1
2
3
4
-Processor Interface
Symbol
P0.0,A0
P0.1,A1
P0.2,A2
P0.3,A3
P0.4,A4
P0.5,A5
P0.6,A6
P0.7,A7
P1.0
P1.1
P1.2
P1.3
INT
RESIN
RESEX
Input (I)
Output (O)
I
I
I
I
I
I
I
I
I/O
I/O
I/O
I/O
O
(OD)
O
I
Function
Address Bus, demultiplexed bus mode.
Transfers addresses from the P-system to the
ELIC.
Port 0, multiplexed bus mode.
Parallel input port. The current data is latched with
the falling edge of RD, DS.
Port 1
4-bit I/O port. Every pin can be configured
individually as input or output. For inputs the
current data is latched with the falling edge of RD,
DS.
Interrupt Request, active low.
This signal is activated when the ELIC requests an
interrupt. Due to the open drain (OD)
characteristic of INT multiple interrupt sources can
be connected together.
Reset Indication
This pin is set to "high", when the ELIC executes
either a power-up reset, a watchdog timer reset,
an external reset (RESEX) or a software system
reset.
Reset External
A "high" forces the ELIC into reset state.
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PEB 20550
PEF 20550
Overview
01.96