PEF20550HV2.1XT Infineon Technologies, PEF20550HV2.1XT Datasheet - Page 110

• Manufacturer Part Number: PEF20550HV2.1XT
• Manufacturer: Infineon Technologies

Specifications of PEF20550HV2.1XT

• Lead Free Status / Rohs Status: Compliant

Transparent mode 1
Non-auto mode
Auto-mode
pin for collision detection. In point-to-point configuration, the C D-pin must be tied to
ground if no "clear to send" function is provided via a modem.
Depending on the features desired, the following registers may also require initializing
before powering up the SACCO:
Table 18
Feature Dependent Register Set-up
Feature
Clock mode 2
Masking selected interrupts
DMA controlled data transfer
Check on receive length
The CCR1 is the final minimum register that has to be programmed to initialize the
SACCO. In addition to defining the serial port configuration, the CCR1 sets the clock
mode and allows the CPU to power-up or power-down the SACCO.
In power-down mode all internal clocks are disabled, and no interrupts are forwarded to
the CPU. This state can be used as standby mode for reduced power consumption.
Table 17
Mode Dependent Register Set-up
The second minimum register to be initialized is the CCR2. In combination with the
CCR1, the CCR2 defines the configuration of the serial port. It also allows enabling the
RFS-interrupt.
If bus configuration is selected, the external serial bus must be connected to the C D-
Semiconductor Group
1 Byte Address
RAH1 = 00
RAH2 = 00
RAL1
RAL2
XAD1
XAD2
RAH1 = 00
RAH2
RAL1
RAL2
110
XBCH
Register(s)
TSAR, TSAC, XCCR, RCCR
MASK
RLCR
H
H
H
Operational Description
2 Byte Address
RAH2
RAH1
RAH2
RAL1
RAL2
XAD1
XAD2
RAH1
RAH2
RAL1
RAL2
RAH1
PEB 20550
PEF 20550
01.96