PEF20550HV2.1XT Infineon Technologies, PEF20550HV2.1XT Datasheet - Page 376

• Manufacturer Part Number: PEF20550HV2.1XT
• Manufacturer: Infineon Technologies

Specifications of PEF20550HV2.1XT

• Lead Free Status / Rohs Status: Compliant

Problem Description:
Assuming the arbiter is in the state FULL SELECTION, it will change to the state
EXPECT FRAME and then RECEIVE FRAME, as soon as the opening flag of the HDLC
frame (frame indication) is detected.
The SACCO_A will then start to copy the received data to the RFIFO. Usually (if there is
enough space for the whole frame + 1 byte) the arbiter would abandon this state at frame
end and enter the state LIMITED SELECTION.
In the case, where there is not enough space for the whole frame + 1 byte, the arbiter
will not get the frame end indication and the D-channel arbiter stays in the state
RECEIVE FRAME.
Explanation:
The reason for this behaviour is, that the frame end indication is send to the arbiter as
soon as the receive status byte (RSTA) is written to the FIFO. So if there is no space for
the RSTA byte in the RFIFO, the arbiter will not receive a frame end indication.
Resulting Behaviour:
Sucessive frames will not be rejected (no blocking information is being send), but lead
to a Receive Frame Overflow interrupt of the ELIC.
This behaviour makes the sending HDLC controller believe, it can continue in sending
new frames, whereas all other channels still get the blocked information.
How to Manage the Situation:
In order to stop the HDLC controller from transmitting and give the other HDLC
controllers a chance to be arbitrated, the arbiter state RECEIVE FRAME must be
abandoned, as soon as the ELIC indicates this situation (e.g. Receive Frame Overflow
interrupt).
This can be achieved by 2 possibilities:
1. Switching the clock mode (CCR1:CM1..0) unequal 3. The result is a change to the
2. Sending a Receive Message Complete command (CMDR = 80) to the SACCO_A.
Note: If the command RESET HDLC receiver (CMDR:RHR = 1) is performed, the arbiter
Semiconductor Group
arbiter state SUSPENDED
This generates internally a Frame End and the arbiter changes to the state LIMITED
SELECTION.
is not reset and stays in the state RECEIVE FRAME until a new frame has been
sent, or the clock mode is changed, as described before.
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Application Notes
PEB 20550
PEF 20550
01.96