PEF20550HV2.1XT Infineon Technologies, PEF20550HV2.1XT Datasheet - Page 322

• Manufacturer Part Number: PEF20550HV2.1XT
• Manufacturer: Infineon Technologies

Specifications of PEF20550HV2.1XT

• Lead Free Status / Rohs Status: Compliant

Examples
In CFI mode 1 the following P channels shall be realized:
Upstream: CFI port 1, timeslot 7:
W:MADR
W:MAAR
Downstream: CFI port 0, timeslot 2, the value ‘0000 0111’ shall be transmitted:
W:MADR
W:MAAR
The next sequence will read the currently received value at DU1, TS7:
W:MAAR
W:MACR
wait for STAR:MAC = 0
R:MADR
Cancelling of a Programmed CFI P Channel:
W:MACR
W:MACR
Semiconductor Group
W:MADR
W:MAAR
W:MACR
= 1111 1111
= 1000 1111
= 0111 1001
= 0000 0111
= 0000 0100
= 0111 1001
= 1000 1111
= 1100 1000
= value
= don’t care
= CFI port and timeslot encoded according to figure 84
= 0111 0000
B
B
B
B
B
B
B
B
= C8
B
= 70
H
; don’t care
; CFI timeslot encoding according to figure 84
; CM code for a P channel (code ‘1001’)
; CFI idle value ‘0000 0111’
; CFI timeslot encoding according to figure 84
; CM code for a P channel (code ‘1001’)
; upstream CFI port and timeslot
; received CFI idle value
; read back command
H
; code ‘0000’ (unassigned channel)
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Application Hints
PEB 20550
PEF 20550
01.96