HI-6121PQMF HOLTIC [Holt Integrated Circuits], HI-6121PQMF Datasheet - Page 10

• Manufacturer Part Number: HI-6121PQMF
• Description: MIL-STD-1553 Remote Terminal ICs
• Manufacturer: HOLTIC [Holt Integrated Circuits]

REGISTERS, Cont.
12
11
10
8
7
6-5
4
3
9
SDSEL
TTCK2
TTCK1
TTCK0
STEX
SRST
——
BCSTINV
UMCINV
Shutdown Select.
These three bits select the time-tag counter clock source from the following options:
Start Execution.
Software Reset.
Not used.
Broadcast Commands Invalid.
Undefined Mode Codes Invalid.
This bit affects terminal response to “transmitter shutdown” mode code commands and only applies
when the MCOPT4 bit in Configuration Register 2 equals logic 0 for automatic shutdown after
“transmitter shutdown” and “selected transmitter shutdown” mode code commands. When MCOPT4
and SDSEL are both logic 0, a valid “transmitter shutdown” mode command automatically disables
the inactive bus transmitter
mode of operation and is the default state of these two bits after
When MCOPT4 is logic 0 and SDSEL is logic 1, “transmitter shutdown” or “selected transmitter
shutdown” mode commands automatically disable just the inactive bus transmitter,
receiver remains enabled
inactive bus (storing received data, etc.), except it does not transmit status or data onto that bus
(”mute terminal”). This mode of operation is not recommended but may be required in some
applications. See MCOPT4 bit in Configuration Register 2 for further information concerning
“transmitter shutdown” and “selected transmitter shutdown” mode commands. Also see Built-In Test
(BIT) Word Register which contains status flags that reflect automatic shutdown status when the
MCOPT4 bit in Configuration Register 2 is logic 0.
Time-Tag Counter Clock Select.
Assertion of this bit initiates RT operation; negation of this bit inhibits or stops RT operation. Upon
STEX assertion, RT parity-address error prevents terminal operation, regardless of the logical state
of the STEX bit. If RT address parity error occurs, the Status Register and Pending Interrupt Register
RTAPF bits will be asserted.
Assertion of this bit immediately initiates the software reset process. This bit should not be set to logic
1 during auto-initialization. This bit is cleared after
being set by the host.
If this bit is high, commands addressed to RT address 31 are treated as invalid: There is no terminal
recognition of commands to RT address 31; there is no RT command response, and no status
updating for the benefit of following “transmit status” or “transmit last command” mode commands. If
this bit is low, commands addressed to RT address 31 are treated as valid broadcast commands.
This bit globally defines whether undefined mode code commands are treated as valid (default) or
invalid commands. This bit applies only to the following undefined mode code commands:
If this bit is low (default state after
valid, and RT response is based on individual mode command settings in the Illegalization Table: If a
TTCK2
0
0
0
0
1
1
1
1
TTCK1
0
0
1
1
0
0
1
1
HOLT INTEGRATED CIRCUITS
Mode Codes 0 through 15 with
Mode Codes16, 18 and19 with
Mode Codes 17, 20 and 21 with
HI-6120, HI-6121
TTCK0
This bit is cleared after
. The terminal fully complies with valid commands received on the
and receiver
0
1
0
1
0
1
0
1
MR
10
pin reset) undefined mode code commands are considered
Clock Source
Time-Tag counter disabled
External clock provided at TTCK input pin
Internally generated 2us clock
Internally generated 4us clock
Internally generated 8us clock
Internally generated 16us clock
Internally generated 32us clock
Internally generated 64us clock
(complete ”bus shutdown”). This is the recommended
MR
MR
master reset and automatically self-resets after
pin master reset.
T/
T/
T/
R
R
R
bit = 0
bit = 0
bit = 1
MR
reset.
but the bus