HI-6121PQMF HOLTIC [Holt Integrated Circuits], HI-6121PQMF Datasheet - Page 77

• Manufacturer Part Number: HI-6121PQMF
• Description: MIL-STD-1553 Remote Terminal ICs
• Manufacturer: HOLTIC [Holt Integrated Circuits]

HOST SERIAL PERIPHERAL INTERFACE, Cont. (HI-6121 ONLY)
HI-6121 SPI COMMANDS
For the HI-6121, each SPI read or write operation begins
with an 8-bit command byte transferred from the host to the
device after assertion of
reception is half-duplex, the host discards the dummy byte
it receives while serially transmitting the command byte.
The HI-6121 SPI command set uses the most significant
command bit to specify whether the command is Read or
Write. The command byte MSB is zero for read
commands, and one for write commands.
FAST-ACCESS COMMANDS FOR REGISTERS 0-15
The SPI command set includes directly-addressed read
and write commands for registers 0 through 15. The 8-bit
pattern for these commands has the general form
where RRRR is the 4-bit register address, and the most
significant bit, W signifies Write when 1, or Read when 0.
These fast-access commands appear at the top of Table 2.
Figures 22 and 23 show read and write timing as it appears
for fast-access register operations. The command byte is
immediately followed by two data bytes comprising the 16-
bit data word read or written. For a register read or write,
CE
RAM AND REGISTER INDIRECT ADDRESSING
Refer to the HI-6121 SPI command set shown in Table 2.
SPI commands other than fast-access use an address
pointer to indicate the address for read or write
transactions.
register address 15, and must be initialized before any
non-fast-access read or write operation.
To set the address pointer, use a fast-access write to
SCK
SPI Mode 0
SI
SO
CE
is negated after the 2-byte data word is transferred.
High Z
MSB
This “primary address pointer” resides at
0
1
W-0-R-R-R-R-0-0
Command Byte
2
CE
3
. Since HI-6121 command byte
FIGURE 22. Single-Word (2-Byte) Read From RAM or a Register
4
5
6
LSB
7
HOLT INTEGRATED CIRCUITS
MSB
0
HI-6120, HI-6121
1
2
Data Byte 0
3
77
4
register 15, consisting of command byte 0xBC followed by
the desired 16-bit memory or register address. The pointer
uses a 15-bit value to access any location in the 32K
address range. The current address pointer value can be
read using a fast-access read command byte 0x3C.
After a 2-byte read/write completion, the internal address
pointer automatically increments to the following register
address. The host may choose to extend the read or write
operation to the next register address by continuing to hold
CE
increment feature can be used to access one or more
sequential register addresses above the command byte
address. Auto-increment applies (ranging to the top of the
address space) as long as SCK continues to be clocked
under continuous
primary address pointer is used for auto-incrementing
multi-word read/write and reaches the top of the address
range (0x7FFF) the next increment will roll over the pointer
value to 0x0000. The host should avoid this situation.
Three single-byte SPI commands modify the current
address pointer value in register 15:
Command
The “Add 4” command may be useful when sequentially
accessing the same word (for example, the Control Word)
in a series of 4-word Descriptor Table entries. The “Add 2”
command might be useful for reading the Interrupt Log
Buffer, comprised of 2-word log entries. In both cases, the
Add command would be probably followed by Read
command 0x40 to read the location addressed by the
5
0xD0
0xD8
0xE0
low while clocking SCK 16 additional times. This auto-
6
LSB MSB
7
0
————————————
Address Pointer Operation
1
add 1 to the current pointer value
add 2 to the current pointer value
add 4 to the current pointer value
CE
2
Data Byte 1
assertion.
3
4
Host may continue to assert
here to read sequential word(s).
Each word needs 16 SCK clocks.
5
Caution:
6
LSB
7
When the
High Z
CE