HI-6121PQMF HOLTIC [Holt Integrated Circuits], HI-6121PQMF Datasheet - Page 34

• Manufacturer Part Number: HI-6121PQMF
• Description: MIL-STD-1553 Remote Terminal ICs
• Manufacturer: HOLTIC [Holt Integrated Circuits]

INTERRUPT LOG BUFFER, Cont.
0x005F
0x005D
0x004F
0x004D
0x005E
0x005C
0x005B
0x005A
0x0057
0x004E
0x004C
0x004B
0x004A
0x0047
0x0058
0x0056
0x0055
0x0054
0x0053
0x0052
0x0050
0x0048
0x0046
0x0045
0x0044
0x0043
0x0042
0x0040
0x0059
0x0051
0x0049
0x0041
INTERRUPT 16
INTERRUPT 16
INTERRUPT 15
INTERRUPT 15
INTERRUPT 14
INTERRUPT 14
INTERRUPT 13
INTERRUPT 13
INTERRUPT 12
INTERRUPT 12
INTERRUPT 11
INTERRUPT 11
INTERRUPT 10
INTERRUPT 10
INTERRUPT 9
INTERRUPT 9
INTERRUPT 8
INTERRUPT 8
INTERRUPT 7
INTERRUPT 7
INTERRUPT 6
INTERRUPT 6
INTERRUPT 5
INTERRUPT 5
INTERRUPT 4
INTERRUPT 4
INTERRUPT 3
INTERRUPT 3
INTERRUPT 2
INTERRUPT 2
INTERRUPT 1
INTERRUPT 1
FIGURE 8. Fixed Address Mapping for Interrupt Log Buffer
Interrupt Address Word
Interrupt Information Word
Interrupt Address Word
Interrupt Information Word
Interrupt Address Word
Interrupt Information Word
Interrupt Address Word
Interrupt Information Word
Interrupt Address Word
Interrupt Information Word
Interrupt Address Word
Interrupt Information Word
Interrupt Address Word
Interrupt Information Word
Interrupt Address Word
Interrupt Information Word
Interrupt Address Word
Interrupt Information Word
Interrupt Address Word
Interrupt Information Word
Interrupt Address Word
Interrupt Information Word
Interrupt Address Word
Interrupt Information Word
Interrupt Address Word
Interrupt Information Word
Interrupt Address Word
Interrupt Information Word
Interrupt Address Word
Interrupt Information Word
Interrupt Address Word
Interrupt Information Word
HOLT INTEGRATED CIRCUITS
HI-6120, HI-6121
34
EXAMPLE: 2-WORD LOG BUFFER ENTRIES
FOR VARIOUS INTERRUPT TYPES...
Example 1: MERR bit is set in Interrupt Enable Register.
An error occurs while transacting a receive command for
subaddress 30:
Address Word = 0x0278 Descriptor Address for Rx Subaddress 30.
Information Word = 0x0400 MERR (interrupt message error) bit = 1.
Example 2: IWA
The IWA bit is set in
to generate an interrupt upon each message occurrence.
A transmit command is received for subaddress 30:
Address Word = 0x02F8 Descriptor Address for Tx Subaddress 30.
Information Word = 0x4000 IWA (interrupt when accessed) bit = 1.
Example 3: ILCMD bit is set in Interrupt Enable Register.
“Illegal Command Detection” is being applied and all
Illegalization Table bits for undefined mode codes are set.
An undefined Mode Code 0 with T/ bit = 0 is received:
Address Word = 0x0300 Descriptor Address for Rx Mode Code 0.
Information Word = 0x0100 ILCMD (interrupt illegal command) bit = 1.
Example 4: TTINT0 bit is set in Interrupt Enable Register.
The Time-Tag counter rolls over from full count 0xFFFF
to 0x0000:
Address Word = 0x0000 (all hardware interrupts reset the IAW)
Information Word = 0x0010 TTINT0 (Time-Tag interrupt 0) bit = 1
The Interrupt Log Address Register
points to this address after Interrupt
15 event occurs. Upon Interrupt 16
completion, device logic reinitializes
the log address pointer to 0x0040
before Interrupt 17 is processed.
Interrupt Log Address Register
is initialized by device logic to
point to this address after
hardware reset (MR) or software reset
bit is set in Interrupt Enable Register.
Transmit Subaddress 30 Control Word
R
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Figure 9 shows where
these addresses occur
in the Descriptor Table.
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