HI-6121PQMF HOLTIC [Holt Integrated Circuits], HI-6121PQMF Datasheet - Page 17

• Manufacturer Part Number: HI-6121PQMF
• Description: MIL-STD-1553 Remote Terminal ICs
• Manufacturer: HOLTIC [Holt Integrated Circuits]

REGISTERS, Cont.
7
6-5
4
3
2
1
0
1553 STATUS WORD BITS REGISTER
This 16-bit register is Read-Write and is fully maintained by the host. The register is cleared after
software reset. All bits are active high. Bits set in this register are reflected in the outgoing MIL-STD-1553 status word.
The”dynamic bus control acceptance” bit is not implemented; this device cannot function as bus controller. The host controls
the Instrumentation, Busy, Terminal Flag, Service Request and Subsystem Flag status word bits by writing to bits 9:0 in this
register. Remote terminal status word responses reflects the assertion of these register bits until negated by the host, unless
the Immediate Clear function (bit 15) is enabled. The position of register bits 4 and 10 correspond to the Broadcast Command
Received (BCR) and Message Error (ME) bits in the terminal status word. Transmit state for the BCR and ME bits in the
terminal’s status word is controlled by the device, based on prior command transactions. This pair of register bits cannot be set
by a host write operation and always read back logic 0, so do not reflect the true status of these status flags.
MSB
15 14 13 12 11 10 9
LBFA, LBFB
0
EECKF
RAMIF
SPIFAIL
TTINT1
TTINT0
RTAPF
0
0
0
0
Initialization EEPROM Checksum Fail Interrupt.
(determined by the Illegalization Table) occurs for a new command. The
and the Interrupt Log is updated. See section entitled “Illegalization Table” for additional information.
SPI Fail Interrupt (HI-6121 only).
The HI-6121 uses a SPI interface for host access. The device operates in SPI Slave mode. If the
SPIFAIL bit is set in the Interrupt Enable register, this bit is asserted each time an incorrect number of
SCK clocks occurs during SPI chip select assertion, The
Log is updated.
Loopback FailBus A and Loopback Fail Bus B Interrupts.
During all transmitted command responses, the device compares words transmitted to the received
and decoded words detected on the bus. If the LBFA or LBFB bit is set in the Interrupt Enable register,
this bit is asserted each time this loopback detects mismatch. The
Interrupt Log is updated.
Time-Tag Interrupt 1.
If the TTINT1 bit is set in the Interrupt Enable register, this bit is asserted each time the free-running
Time-Tag counter value matches the value stored in the Time-Tag Utility Register. The
is asserted and the Interrupt Log is updated.
Time-Tag Interrupt 0.
If the TTINT0 bit is set in the Interrupt Enable register, this bit is asserted each time the free-running
Time-Tag counter value rolls over from full count 0xFFFF to 0x0000. The
and the Interrupt Log is updated.
RTAddress Parity Fail Interrupt.
This bit is asserted when RT address and parity bits latched in the Operational Status Register do not
exhibit odd parity (odd number of bits having logic 1 state). Because the RTAPF bit is always set in the
Interrupt Enable register, the
error occurs, the RT will not begin operation, regardless of the state of the Control Register STEX bit.
This bit is asserted if serial EEPROM checksum failure occurs during auto-initialization. Because the
EECKF bit is always set in the Interrupt Enable register, the
Interrupt Log is updated.
RAM Initialization Fail Interrupt.
This bit is asserted after auto-initialization if an initialized RAM location does not match its 2
corresponding serial EEPROM locations. Because the RAMIF bit is always set in the Interrupt Enable
register, the
8
0
7
0
6
INTHW
0
5
0
4
HOLT INTEGRATED CIRCUITS
output is asserted and the Interrupt Log is updated.
3
2
(0x0007)
HI-6120, HI-6121
0
1
INTHW
0
LSB
17
output is asserted and the Interrupt Log is updated. When parity
* STATUS BIT AUTOMATICALLY
CONTROLLED BY DEVICE
INTHW
INTHW
output is asserted and the Interrupt
INTMES
MR
output is asserted and the
INTMES
INTHW
pin Master Reset or SRST
output is asserted and the
output is asserted
output is asserted
INTHW
output