HI-6121PQMF HOLTIC [Holt Integrated Circuits], HI-6121PQMF Datasheet - Page 16

• Manufacturer Part Number: HI-6121PQMF
• Description: MIL-STD-1553 Remote Terminal ICs
• Manufacturer: HOLTIC [Holt Integrated Circuits]

REGISTERS, Cont.
DESCRIPTOR TABLE BASE ADDRESS REGISTER
This 16-bit register is Read-Write and is fully maintained by the host. This register is loaded with 0x0200 after
reset or SRST software reset. The host maintains this register to specify the starting address for the Descriptor Table. For fast
context switching, the host may initialize multiple Descriptor Tables, then update this register to load the new base address
when the active Descriptor Table changes. The base address must be chosen with bits 7:0 = 00000000. These bits (and the
highest address bit) cannot be set in the register. The primary Descriptor Table (enabled at reset) should reside at address
space 0x0200 to 0x03FF. Other tables (if used) could begin at address multiples of 0x0200, like 0x0400 and 0x0600. Bit 15 and
bits 7:0 cannot be set and will always read logic 0.
PENDING INTERRUPT REGISTER
This 16-bit register is Read-Only. It is cleared after
corresponding bit is set in the Interrupt Enable Register when a predetermined interrupt-causing event occurs, these actions
occur: (1) a pending interrupt bit is set in this register, (2) the
type, (3) the interrupt is registered in the Interrupt Log. To simplify host interrupt management, when the host reads this
register, the Pending Interrupt Register automatically resets to 0x0000 and (if level interrupts are enabled by the INTSEL
configuration bit) the
behavior, also see descriptions for Interrupt Enable register and Interrupt Log Address register, and refer to the later section
entitled “Interrupt Management”.
Bit No.
15
14
13
12-11
10
9
8
MSB
MSB
15 14 13 12 11 10 9
15 14 13 12 11 10 9
0
A
Mnemonic Interrupt Type
IXEQZ
IWA
IBR
——
MERR
——
ILCMD
A
DESCRIPTOR TABLE BASE ADDR 15:0
A
X
X
A
INTMES
A
Index Equal Zero Interrupt.
If the IXEQZ bit is set in the Interrupt Enable register and the subaddress descriptor Control Word
allows the IXEQZ interrupt, this bit is asserted for (a) subaddresses using indexed buffer mode when
the index decrements from 1 to 0, or (b) subaddresses using circular buffer modes when the pre-
determined number of messages has been transacted. The
Interrupt Log is updated.
Interrupt When Accessed.
If the IWA bit is set in the Interrupt Enable register and the subaddress descriptor Control Word allows
the IWA interrupt, this bit is asserted each time a valid legal message is transacted for the
subaddress. The
Broadcast Command Received Interrupt.
If the IBR bit is set in the Interrupt Enable register and the subaddress descriptor Control Word allows
the IBR interrupt, this bit is asserted each time a valid legal broadcast message is transacted for the
subaddress. The
Not used.
Message Error Interrupt.
If the MERR bit is set in the Interrupt Enable register, this bit is asserted when a message error is
detected. Errors can be caused by Manchester encoding problems or protocol errors. The
output is asserted and the Interrupt Log is updated.
Not used.
Illegal Command Interrupt.
If the ILCMD bit is set in the Interrupt Enable register, this bit is asserted each time an illegal message
X
A
A
8
8
and/or
7
0
7
6
0
6
INTHW
0
5
5
4
INTMES
INTMES
0
4
HOLT INTEGRATED CIRCUITS
(0x0006)
3
0
3
output pins are automatically negated. For further information on interrupt
0
2
2
HI-6120, HI-6121
output is asserted and the Interrupt Log is updated.
output is asserted and the Interrupt Log is updated.
MR
1
0
1
0
0
0
pin master reset, but is not affected by SRST software reset. If the
LSB
LSB
16
INTMES
(0x0005)
or
INTHW
output is asserted, depending on interrupt
INTMES
output is asserted and the
MR
pin master
INTMES