HI-6121PQMF HOLTIC [Holt Integrated Circuits], HI-6121PQMF Datasheet - Page 73

• Manufacturer Part Number: HI-6121PQMF
• Description: MIL-STD-1553 Remote Terminal ICs
• Manufacturer: HOLTIC [Holt Integrated Circuits]

RESET AND INITIALIZATION, Cont.
different method is used for writing the serial EEPROM, the
twos-complemented checksum (described earlier) must
be saved in EEPROM locations corresponding to device
RAM address 0x0020.
A compatible serial EEPROM uses a SPI interface for byte-
access read and write operations. Sixteen-bit register and
RAM values in the HI-612X are stored as upper and lower
bytes in the EEPROM, in “big endian” fashion. For
example, the upper byte for register address 0x0000 is
stored at EEPROM address 0x0000 while the lower byte is
stored at EEPROM address 0x0001. A 64K x 8 EEPROM is
required to store the entire 32K x 16 address range.
Serial EEPROM data mapping follows the device memory
map shown in Figure 1. The single exception: two
EEPROM locations corresponding to device RAM address
0x0020 must contain the expected checksum value. The
serial EEPROM used for auto-initialization should be fully
written to cover the HI-6120/21 upper address limit of
0x7FFF (or 0x03FF, depending on the state of the EE1K
input pin). Ideally the EEPROM image will reflect a post-
MR
written to reset-cleared registers or RAM as a result of
command processing.
SOFTWARE RESET
Software reset is initiated by a host write that sets the
SRST bit in Configuration Register 1. This bit is set
automatically when a “Reset Remote Terminal” mode
command is received while the MCOPT0 bit is set in
Configuration Register 2 (0x0002). Software reset causes
immediate reset without overwriting registers or tables that
were initialized by the host to define terminal behavior.
Changes to r
19.
initialization from serial EEPROM. Once the SRST bit in
Configuration Register 1 is asserted, the following steps
are performed:
1. The READY, ACTIVE,
pins are negated. Terminal execution stops while
SRST reset is underway. Command processing is
terminated.
hardware encoder are cleared.
and Broadcast Command Received flags in the
internal status register used for MC2 or MC18 mode
command responses are not affected by SRST.
2.
reinitialized to the base address 0x0200.
registers are cleared: the 1553 Status Word Bits
register
test registers 0x0016 to 0x0019.
3.
the contained RTAPF bit is not changed.
reinstates any bus previously shutdown by mode code
commands MC4 or MC20 (decimal). If the
Flag status bit was previously inhibited by mode
reset followed by fresh initialization with nothing
Software reset cannot initiate automatic self-
The BIT Word Register (0x0014) is cleared, except
The Descriptor Base Address register (0x0005) is
(0x0007)
egisters and RAM are summarized in Figure
The hardware bus decoders and
, the
Time-Tag register (0x0008) and
INTMES
The Message Error
and
INTHW
HOLT INTEGRATED CIRCUITS
The following
Terminal
HI-6120, HI-6121
output
This
73
RESET REMOTE TERMINAL MODE CODE
Mode code MC8 with T/ bit = 1 should reset the Remote
Terminal. After Status Word transmission, the device
automatically resets the status Message Error (ME) and
Broadcast Command received (BCR) bits in its internal
status register. Bits 0, 14 and 15 are reset in the BIT Word
register at address 0x0014. If either transmitter was
shutdown by a previous mode code MC4 or MC20, the
shutdown condition is overridden. If the Terminal Flag (TF)
status bit was inhibited, the inhibit is reset. This command
does not reset any of the host-programmed registers that
configure the terminal for operation.
To complete the reset process, the host must assert either
MR
assert the SRST bit in Configuration Register 1 to execute
software reset. Since MC8 requires host interaction, most
applications will probably utilize the IWA interrupt to alert
the host when valid MC8 is received.
Per MIL-STD-1553B appendix 30.4.3, any reset initiated
by the “Reset Remote Terminal” mode command should
be completed within 5 ms following transmission of the
Status Word. Overall reset time includes internal device
initialization, either host initialization or auto-initialization.
Overall time to complete reset initiated by the
Remote Terminal”
response speed and application complexity.
command MC6, inhibit is cleared: The Terminal Flag
status bit will be transmitted whenever bit 0 is set in the
1553 Status Word Bits Register.
4. All 128 descriptor table Control Words are modified
to reset the DBAC, DPB, MKBUSY and BCAST bits.
Subaddresses or mode codes using ping-pong or
single message index mode (INDX = 0) are ready for
immediate operation after SRST reset is complete.
However the device cannot reinitialize the Descriptor
Table to restore multi-message block transfers, for
indexed buffer mode when initial INDX value was non-
zero, or for either circular buffer mode.
5. The device asserts the READY output pin. Terminal
operation automatically resumes if the STEX bit in
Configuration Register 1 was set before SRST
occurred.
6. After READY assertion, the host may reset STEX,
then reinitialize all or part of the Descriptor Table. The
host can reinitialize the Descriptor Table for
subaddresses using multi-message block transfers
(Circular Buffer Mode 1, Circular Buffer Mode 2 or
Indexed Buffer Mode with initial non-zero INDX.) The
host can also reinitialize transmit data in the assigned
transmit subaddress data buffers. Data buffers in RAM
contain data values loaded before SRST occurred.
The host can clear or overwrite this old data. The host
can then assert the STEX bit in Configuration Register
1 to restart terminal operation.
master reset (with or without auto-initialization) or
mode command MC8 is affected by host
R
“Reset