HI-6121PQMF HOLTIC [Holt Integrated Circuits], HI-6121PQMF Datasheet - Page 74

• Manufacturer Part Number: HI-6121PQMF
• Description: MIL-STD-1553 Remote Terminal ICs
• Manufacturer: HOLTIC [Holt Integrated Circuits]

RESET AND INITIALIZATION, Cont.
SERIAL EEPROM PROGRAMMING UTILITY
The HI-6120 or HI-6121 can program a serial EEPROM via
the dedicated EEPROM SPI port for subsequent auto-
initialization events. The device copies host-configured
registers and RAM (configuration tables and possibly data
buffers) to serial EEPROM.
Compatible SPI serial EEPROMs are 3.3V, operate in SPI
modes 1 or 3 and and have 128-byte pages. The serial SPI
data is clocked at 8.3 MHz SCK frequency.
EEPROM can restore the lower 1K x 16 device address
space.
device address space.
A deliberate series of events initiates copy of data from HI-
6120 or HI-6121 to serial EEPROM. This reduces the
likelihood of accidental EEPROM overwrites. This series
of events must occur to initiate programming:
1A.
following
EEPROM copy:
TXINHB pins in logic zero state, apply
reset and wait for READY output assertion. Verify that
the
assertion, indicating likely RT address parity error at
the RTA4:0 and RTAP pins. Using known good
parameters, the host initializes device registers, the
RAM descriptor table and transmit data buffers (if
necessary). Do not assert STEX. Go to step 2.
1B.
the baseline for a new EEPROM configuration:
W
and TXINHB pins in logic zero state, apply
reset and wait for READY output assertion. Verify that
the
remain low) at READY assertion. Confirm that the
RTAPF, EECKF and RAMIF bits are all logic 0 in the
Operational Status Register 0x0002. If the STEX bit in
Configuration Register 1 was set by auto-initialization,
reset it now. Modify register and RAM values to reflect
the new changes. Go to Step 2.
2. IMPORTANT: Any processing of valid bus
commands between
will cause auto-initialization checksum failure later,
due to non-zero values written to read-only registers
as a result of command processing. The
enter EEPROM copy mode at step 3 if valid command
reception caused
reset occurred.
Register 1 also locks-out EEPROM copy mode at
programming step 3.
3. The host writes one of two 2-part “unlock codes” to
RAM address 0x0020. The two unlock codes perform
identical EEPROM programming with the exception of
ith the AUTOEN pin in logic 1 state and the TXINHA
A 64K x 8 EEPROM can restore the entire 32K x 16
If using the existing EEPROM configuration as
INTHW
INTHW
If using a fresh host initialization immediately
MR
output does not pulse low (or go and
output does not pulse low at READY
If set, the STEX bit in Configuration
master reset as the basis for
ACTIVE output assertion after
With the AUTOEN, TXINHA and
MR
or
master reset and this point
device will not
HOLT INTEGRATED CIRCUITS
MR
MR
A 2K x 8
HI-6120, HI-6121
master
master
MR
74
The address range copied during EEPROM programming
depends on the state of the EE1K input pin when rising
edge occurs on the EECOPY input:
the programmed state for the STEX bit in
Configuration Register 1.
In either case, the two unlock writes must occur
without intervening access to other device addresses,
except Memory Address Pointer 0x000F for HI-6121.
4. The EECOPY input pin is driven high for at least 1
ms, then driven low. In response, the READY output
goes low while EEPROM memory is written.
Programming commences. The unlock code at
address 0x0020 is cleared, then device register and
RAM contents are written to the serial EEPROM.
During programming, the twos-complemented
checksum is tallied for the entire address range being
programmed (1K or 32K words), excluding addresses
0x0002, 0x0006, 0x0008, 0x0014 and 0x0020. At
EEPROM programming completion, the final
checksum is stored in the pair of EEPROM locations
corresponding to device RAM address 0x0020. The
value written to EEPROM is actually the twos-
complement of the memory checksum, (
+ 1). The value in EEPROM is used for error detection
when performing auto-initialization. (The host can only
access the stored value immediately after an auto-
initialization sequence is performed. The twos-
complement EEPROM checksum value will be copied
into RAM address 0x0020.)
5. When the READY output goes high,
copy is complete
Configuration Register 1.
If EE1K is high when EECOPY is asserted,
1K x 16 address range from 0x0 to 0x03FF is copied
from device registers and RAM to EEPROM. This
includes all registers, all configuration tables in RAM
and the primary Descriptor Table in RAM at address
0x0200 to 0x03FF. The 1K x 16 write to EEPROM
requires up to 65 ms.
If EE1K is low when EECOPY is asserted,
32K x 16 address range from 0x0 to 0x7FFF is copied
If auto-initialize should program Configuration
Register 1 STEX bit to logic 0,
0x0020 is first written 0xA5F0, then a second load
to 0x0020 overwrites the value just written with
0x5F0A.
If auto-initialize should program Configuration
Register 1 STEX bit to logic 1,
0x0020 is first written
to 0x0020 overwrites the value just written with
0xA0F5.
. T
he STEX bit is reset in device
0x5A0F
, then a second load
RAM address
RAM address
CHECKSUM
EEPROM
the entire
the lower