HI-6121PQMF HOLTIC [Holt Integrated Circuits], HI-6121PQMF Datasheet - Page 26

• Manufacturer Part Number: HI-6121PQMF
• Description: MIL-STD-1553 Remote Terminal ICs
• Manufacturer: HOLTIC [Holt Integrated Circuits]

REGISTERS, Cont.
4
3
2
1
0
LOOPBACK TEST TRANSMIT DATA REGISTER
This 16-bit register is Read-Write and is fully maintained by the host. This register is cleared after
affected by SRST software reset. The value contained in this register is used when performing digital loopback testing. See
Test Control Register, 0x0016, for additional information.
LOOPBACK TEST RECEIVE DATA REGISTER
This 16-bit register is Read-Only. This register is cleared after
Data is written to this register when performing digital loopback testing. See Test Control Register, 0x0016, for additional
information.
COMMAND RESPONSES
A brief review of MIL-STD-1553 commands and responses
is appropriate here to establish terminology used in the
rest of this data sheet. Shown in Figure 2, each command
word is comprised of a sync field, three 5-bit data fields, a
single bit denoting Transmit /
with a parity bit. The hardware decoder uses the sync field
to determine word type (command vs. data). Word validity
MSB
MSB
15 14 13 12 11 10 9
15 14 13 12 11 10 9
15 14 13 12 11 10 9
15 14 13 12 11 10 9
LOOPBACK TEST TRANSMIT DATA REGISTER 15:0
LOOPBACK TEST RECEIVE DATA REGISTER 15:0
LBSYNC
LBBUSEL Loopback Test Bus Select.
LBSTART Loopback Test Start.
LBPASS
LBFAIL
Loopback Test Word Sync Select.
When the LBSYNC bit is high, the loopback test word is transmitted with command sync. When the
When this bit is low, loopback testing occurs on Bus A. When this bit is high, loopback testing occurs
Writing logic 1 to this bit initiates the loopback test selected by register bits 2, 6 and 7. The LBSTRT bit
Loopback Test Pass.
Device logic asserts this bit when the selected RAM test completes without error. This bit is
Loopback Test Fail.
Device logic asserts this bit when failure occurs while performing the selected loopback test. Failure
transmitted onto and received from the selected external MIL-STD-1553 bus.
LBSYNC bit is low, the loopback test word is transmitted with data sync.
on Bus B.
can only be set if the external TEST pin is already asserted, and is automatically cleared upon test
completion. Register bits 3-4 indicate pass / fail test result.
automatically cleared when LBSTRT bit 5 is set.
is comprised of Manchester encoding error, parity error, wrong sync type or data mismatch. This bit is
automatically cleared when LBSTRT bit 5 is set.
8
8
8
8
Receive
7
7
7
7
6
6
6
6
direction and ends
5
5
5
5
4
4
4
4
HOLT INTEGRATED CIRCUITS
3
3
3
3
2
2
2
2
HI-6120, HI-6121
1
1
1
1
0
0
0
0
LSB
LSB
(0x0019)
26
MR
(0x0018)
pin master reset, but is not affected by SRST software reset.
is based on proper sync encoding, Manchester II
encoding, correct bit count and correct odd parity for the 16
data bits. Once a valid word with command sync is found,
the sync and parity are stripped before the command’s 16
data bits are stored for further processing.
MR
pin master reset, but is not