HI-6121PQMF HOLTIC [Holt Integrated Circuits], HI-6121PQMF Datasheet - Page 41

• Manufacturer Part Number: HI-6121PQMF
• Description: MIL-STD-1553 Remote Terminal ICs
• Manufacturer: HOLTIC [Holt Integrated Circuits]

DESCRIPTOR TABLE, Cont.
DIFFERENT DATA BUFFER OPTIONS FOR
Data buffer options for mode code commands differ from options offered for subaddress commands. Mode commands cannot
use either circular data buffer method, but may
Index mode (INDX = 0) is suitable in many applications. An alternative called
(SMCP) may be globally applied for all mode code commands.
To use single (indexed) buffer or double (ping-pong) buffer for mode commands, the
logic 0. The Control Word PPEN bit for each mode command determines whether ping-pong or indexed buffering is used.
To use Simplified Mode Command Processing, the SMCP bit in Configuration Register 1 is set to logic 1. The Control Word
PPEN bit for mode commands is “don’t care” (no longer specifies index or ping-pong buffer mode) because Simplified Mode
Command Processing stores mode command data and message information words directly within each mode command’s
redefined Descriptor Table block. When
not contain data pointers to reserved buffers elsewhere in the shared RAM. Instead, each 4-word descriptor block itself
contains the message information word, the time-tag word and the data word transacted for each mode command (for mode
codes 16-31 decimal).
When
command Control Word. Interrupt control and response is not affected by the SMCP option.
Processing is
RECEIVE MODE CONTROL WORD
Receive Mode Control Words apply when the command word T/ bit equals zero (receive) and the subaddress field has a
value of 0 or 31 (0x1F).
activity status to the host. It is initialized by the host before terminal execution begins. Bits 8-11 cannot be written by the host;
these bits are updated by the device during terminal execution, that is, when Configuration Register 1 STEX bit equals 1. The
host can write bit 2 only when STEX equals zero; bits 3 and 12-15 can be written anytime. This register is cleared to 0x0000 by
MR
Control Word address, the DBAC bit is reset.
When single-message indexed buffering or ping-pong buffering is used instead of SMCP (Simplified Mode Code Processing),
the transmit mode Control Word looks like this:
When SMCP applies, the number of active mode Control Word bits is reduced:
Bit No.
15
MSB
MSB
master reset. Software reset (SRST) clears just the DBAC, DPB and BCAST bits. Following any host read cycle to the
15 14 13 12 11 10 9
15 14 13 12 11 10 9
H
H
Simplified Mode Command Processing
H
H
Mnemonic Function
IXEQZ
H
H
fully presented in the later data sheet section entitled “Mode Code Commands.”
H
H
D1 D
D1 X
The descriptor Control Word defines terminal command response and interrupt behavior, and conveys
SMCP Disabled
SMCP Enabled
Interrupt When Index Equals Zero.
If the Interrupt Enable Register IXEQZ bit is high, assertion of this bit enables generation of an
interrupt for mode code commands using indexed buffer mode when the INDX value decrements
from 1 to 0. Upon completion of command processing that results in INDX = 0, when IXEQZ interrupts
D
D
D
X
8
8
X
X
7
7
X
X
6
6
SMCP is enabled, mode code command descriptor blocks (in the Descriptor Table) do
X
X
5
5
X
X
4
4
HOLT INTEGRATED CIRCUITS
MODE CODE COMMANDS
H
X
3
3
use double (ping-pong) buffering or single (indexed) buffering.Single message
is used, the range of active bits is reduced in each receive or transmit mode
X
H
2
2
HI-6120, HI-6121
X
X
1
1
X
X
0
0
LSB
LSB
41
R
D1
D1
H
D
H
D
X
X
Bit maintained by host
Bit maintained by device
Bit set by device, reset by host read cycle
Bit is not used, may read logic 0 or 1
Bit maintained by host
Bit maintained by device
Bit set by device, reset by host read cycle
Bit is not used, may read logic 0 or 1
Simplified Mode Command Processing
SMCP bit in Configuration Register 1 is
Simplified Mode Command