HI-6121PQMF HOLTIC [Holt Integrated Circuits], HI-6121PQMF Datasheet - Page 6

• Manufacturer Part Number: HI-6121PQMF
• Description: MIL-STD-1553 Remote Terminal ICs
• Manufacturer: HOLTIC [Holt Integrated Circuits]

FUNCTIONAL OVERVIEW
The Holt HI-6120 or HI-6121 provides a complete Remote
Terminal (RT) interface between a host and a MIL-STD-
1553B dual redundant data bus. It automatically handles all
aspects of the MIL-STD-1553 protocol, namely,
encoding/decoding, message formatting, error checking,
message data buffering, protocol checking, illegalization
and default terminal responses. Internal static RAM is
shared by the host and device logic, providing efficient
storage for message data and information about messages,
updated after each message transaction. The shared RAM
also contains host-initialized tables that define terminal
operation.
Two options are offered for host interface. The HI-6120 uses
a 16-bit tri-state data bus, ideally suited for memory-mapped
host processor operation. The HI-6121 uses a 3-wire Serial
Peripheral Interface (SPI) with powerful SPI command set.
Registers occupy the lowest 32 addresses of the 32K
memory address space. Internal registers (or contained bit
fields) are partitioned as read-only or read-write so the host
can exercise configuration and control without risk of
misconfiguration caused by accidental writes to device-
maintained registers or bit fields.
Dedicated output pins convey status to the host, and
generate host interrupts for preselected events.
processing messages, internal registers and transmit data
buffers in shared RAM must be initialized by the host to
define the desired message responses. Optional auto-
initialization using parameters in external EEPROM can
replace host initialization.
SHARED RAM UTILIZATION
Descriptor Table
The host-initialized Descriptor Table, residing in shared
RAM, defines terminal response to valid commands. The
table is comprised of 4-word Descriptor Blocks. Each of 32
subaddresses and 32 mode code values has two descriptor
blocks, one for transmit and one for receive, for a total of 128
descriptor blocks. The first word in each descriptor block
defines message options (interrupt selections, data buffer
mode, etc.). E
word counts messages)
allocated data storage in shared RAM. After Master Reset is
negated and before message processing, the host must
initialize descriptor blocks for each utilized subaddress and
mode code. Unused subaddresses and unimplemented
mode codes may be illegalized (see below). The Descriptor
Table Base Address Register is initialized with the starting
address of the Descriptor Table. Multiple Descriptor Tabes
can be used for fast context switching, with the active table
designated by the base address register.
xcept for Indexed buffer mode (where one
the remaining three words point to
HOLT INTEGRATED CIRCUITS
HI-6120, HI-6121
Before
6
Illegalization Table
Optional illegal command detection utilizes an Illegalization
Table in the shared RAM. The table can illegalize any logical
combination of 11 command word bits for subaddress,
bit and word count (or mode code), plus broadcast vs non-
broadcast status, resulting in a total of 4,096 possible
combinations. The Illegalization Table Base Address
Register is initialized with the table’s start address. Terminal
response to an illegal command sets “message error” status
and transmits Status Word only. If illegal command detection
is not used (that is, no “illegal” entries in Illegalization Table),
the terminal responds “in form” to all valid commands.
Message Data Buffers
After master reset, all locations in shared memory are reset
to 0000 hex. Ordinary transmit or receive commands
transfer 1 to 32 data words. These are called “subaddress
commands,” distinguishing them from “mode code
commands,” described in the next paragraph. By initializing
the Descriptor Table, the host allocates space in shared
RAM for storing message data words and message
information words. Data pointers in the table assign
separate data buffer addresses in memory for each
command. Data storage arrangement differs by choice of
data buffer method. Two examples are shown for each of the
four buffer modes in Figures 11-18. After successfully
transacting a message with one or more received data
words, the RT writes into the assigned data buffer. While
transacting a message with one or more transmitted data
words, the RT reads data for transmission from the assigned
data buffer. Before transmit commands occur, the host
should write desired data into assigned transmit data buffers
in shared RAM. Transmit subaddress data buffers can be
optionally loaded by auto-initialization.
Storage for Mode Code Commands
MIL-STD-1553 defines “mode code commands” that are
used for command and control, instead of data transfer. The
various “mode commands” transfer a single data word, or no
data word at all. The user has two choices for storing mode
command data: (1) similar to subaddress command data,
mode command data can be stored in RAM data buffers
assigned by the host-initialized Descriptor Table, or (2)
When “simplified mode command processing” is chosen,
mode command data is stored within the Descriptor Table
itself. Just six defined mode commands transfer a data word;
thus, option 2 is often preferred since initialization is easier.
Consistent, predictable terminal responses can be set up for
all mode commands, including the reserved and undefined
mode codes. An option bit in Configuration Register 1
globally sets whether the 22 undefined mode commands are
treated as illegal (RT response dependent on command’s
Illegalization Table setting) or invalid (no RT response
whatsoever, and no RT status change).
T/R