HI-6121PQMF HOLTIC [Holt Integrated Circuits], HI-6121PQMF Datasheet - Page 9

• Manufacturer Part Number: HI-6121PQMF
• Description: MIL-STD-1553 Remote Terminal ICs
• Manufacturer: HOLTIC [Holt Integrated Circuits]

REGISTERS
Residing at the start of the memory address space, 32 addresses are reserved for HI-6120 and HI-6121 registers. Register
addresses overlay the shared RAM address space, but are separate from the shared dual-port RAM. All register bits are active
high. Unless otherwise indicated, all registers are reset in software to the logic zero condition after Master Reset (except any
bits reflecting the state of input pins). For all registers, bit 15 is the most significant:
CONFIGURATION REGISTER 1
This 16-bit register is Read-Write and is fully maintained by the host. All bits are active high.
Master Reset. After SRST software reset, the SRST bit is reset; the remaining bits are unchanged.
Bit No.
15
14
13
MSB
15 14 13 12 11 10 9
Mnemonic Function
INHBUSA
INHBUSB
INTSEL
Register
Number
26
11-14
10
15
16
17
18
19
20
21
22
23
24
25
0
1
2
3
4
5
6
7
8
9
-31
Interrupt Mode Select.
Bus A Inhibit.
When set, this bit disables transmit and receive for Bus A. This bit is logically ORed with the TXINHA
input signal to control Bus A transmitter enablement. Bus A transmission is disabled if the INHBUSA
register bit or TXINHA input pin is asserted. The TXINHA pin does not affect the Bus A receiver.
Bus B Inhibit.
When set, this bit disables transmit and receive for Bus B. This bit is logically ORed with the TXINHB
input signal to control Bus B transmitter enablement. Bus B transmission is disabled if the INHBUSB
register bit or TXINHB input pin is asserted. The TXINHB pin does not affect the Bus B receiver.
When this bit is low, pulse interrupt outputs are selected for
this bit is high, level interrupts are enabled which require host acknowledgment for interrupt pin reset.
8
7
X
6
0x000B-0x000E
0x001A-0x001F
X
5
Address
(0x0000)
0x0000
0x0001
0x0002
0x0003
0x0004
0x0005
0x0006
0x0007
0x0008
0x0009
0x000A
0x000F
0x0010
0x0012
0x0013
0x0014
0x0015
0x0016
0x0017
0x0018
0x0019
0x0011
4
Hex
HOLT INTEGRATED CIRCUITS
3
2
HI-6120, HI-6121
1
0
LSB
9
Register Name
Configuration Register 1
Configuration Register 2
Operational Status Register
Current Command Register
Current Control Word Address Register
Descriptor Table Base Address Register
Pending Interrupt Register
1553 Status Word Bits Register
Time-Tag Register
Interrupt Log Address Register
Current Message Information Word Address Register
Reserved
Memory Address Pointer (HI-6121 Only)
Interrupt Enable Register
Time-Tag Utility Register
Bus A Select Register
Bus B Select Register
Built-In Test (BIT) Word Register
Alternate Built-In Test (BIT) Word Register
Reserved
Test Control Register
Loopback Test Transmit Data Register
Loopback Test Receive Data Register
Reserved
INTMES
This register is cleared after
and
INTHW
output pins. When
MR
pin