HI-6121PQMF HOLTIC [Holt Integrated Circuits], HI-6121PQMF Datasheet - Page 76

• Manufacturer Part Number: HI-6121PQMF
• Description: MIL-STD-1553 Remote Terminal ICs
• Manufacturer: HOLTIC [Holt Integrated Circuits]

HOST SERIAL PERIPHERAL INTERFACE (HI-6121 ONLY)
In the HI-6121, internal RAM and registers occupy a 32K x
16 address space. The lowest 32 addresses access
registers and the remaining addresses access RAM
locations. Timing is identical for register operations and
RAM operations via the serial interface, and read and write
operations have likewise identical timing.
SERIAL PERIPHERAL INTERFACE (SPI) BASICS
The HI-6121 uses an SPI synchronous serial interface for
host access to registers and RAM. Host serial
communication is enabled through the Chip Enable (
pin, and is accessed via a three-wire interface consisting of
Serial Data Input (SI) from the host, Serial Data Output
(SO) to the host and Serial Clock (SCK). All programming
cycles are completely self-timed, and no erase cycle is
required before write.
The SPI (Serial Peripheral Interface) protocol specifies
master and slave operation; the HI-6121 operates as an
SPI slave.
The SPI protocol defines two parameters, CPOL (clock
polarity) and CPHA (clock phase). The possible
CPHA
Without describing details of the SPI modes, the HI-6121
operates in the two modes where input data for each
device (master and slave) is clocked on the rising edge of
SCK, and output data for each device changes on the
falling edge. These are known as SPI Mode 0 (CPHA = 0,
CPOL = 0) and SPI Mode 3 (CPHA = 1, CPOL = 1). Be sure
to set the host SPI logic for one of these modes.
The difference between SPI Modes 0 and 3 is the idle state
for the SCK signal, which is logic 0 for Mode 0 state and
logic 1 for Mode 3 state (see figure 20). There is no
SCK (SPI Mode 0)
SCK (SPI Mode 3)
SI
SO
CE
FIGURE 21. Generalized Single-Byte Transfer Using SPI Protocol, SCK is Shown for SPI Modes 0 and 3
combinations define four possible "SPI Modes."
High Z
MSB
MSB
0
0
1
1
HOLT INTEGRATED CIRCUITS
HI-6120, HI-6121
CPOL-
2
2
CE
)
76
3
3
configuration setting in the HI-6121 to select SPI Mode 0 or
Mode 3 because compatibility is automatic.
point, the HI-6121 data sheet only shows the SPI Mode 0
SCK signal in timing diagrams.
The SPI protocol transfers serial data as 8-bit bytes. Once
CE
latch input data into the master and slave devices, starting
with each byte’s most-significant bit. The HI-6121 SPI can
be clocked at 16 MHz.
Multiple bytes may be transferred when the host holds
low after the first byte transferred, and continues to clock
SCK in multiples of 8 clocks.
enable terminates the serial transfer and reinitializes the
HI-6121 SPI for the next transfer. If
full byte is clocked by SCK, the incomplete byte clocked
into the device SI pin is discarded.
Two byte transfers are needed for SPI exchange of 16-bit
register values or RAM data. “Big endian” byte order is
used for SPI data transfers. T
is transferred before the low order byte (bits 7:0).
In the general case, both master and slave simultaneously
send and receive serial data (full duplex) per Figure 21
below. However the HI-6121 operates half duplex,
maintaining high impedance on the SO output, except
when actually transmitting serial data. When the HI-6121
is sending data on SO during read operations, activity on
its SI input is ignored. Figures 22 and 23 show actual
behavior for the HI-6121 SO output.
chip enable is asserted, the next 8 rising edges on SCK
4
4
5
5
6
6
he high order byte (bits 15:8)
A rising edge on
LSB
LSB
CE
7
7
goes high before a
Beyond this
High Z
CE
chip
CE