HI-6121PQMF HOLTIC [Holt Integrated Circuits], HI-6121PQMF Datasheet - Page 25

• Manufacturer Part Number: HI-6121PQMF
• Description: MIL-STD-1553 Remote Terminal ICs
• Manufacturer: HOLTIC [Holt Integrated Circuits]

REGISTERS, Cont.
10
9
8
7-6
5
RBSTRT
RBPASS
RBFAIL
——
LBALOG
RAM BIST Start.
Writing logic 1 to this bit initiates the RAM BIST test selected by register bits RBSEL2:0. The RBSTRT
RAM BIST Pass.
Device logic asserts this bit when the selected RAM test completes without error. This bit is
RAM BIST Fail.
Device logic asserts this bit when failure occurs while performing the selected RAM test. This bit is
Not Used.
Loopback Test Analog.
The device supports either digital or analog loopback testing for either bus transceiver. When the
Description of the RAM BIST “PATTERN” test selected when register bits RBSEL2:0 = 001:
Note: Test read /write accesses to addresses 0x0000 - 0x001F involve 32 RAM locations not
accessible to the host. These accesses do not affect the host-accessible registers, overlaying the
same address range.
1. Write 0x0000 to all RAM locations, 0x0000 through 0x7FFF
2. Repeat the following sequence for each RAM location from 0x00000 through 0x7FFF:
3. Write 0xFFFF to all RAM locations, 0x0000 through 0x7FFF
4. Repeat the following sequence for each RAM location from 0x00000 through 0x7FFF:
5. Write each cell’s memory address into each RAM location from 0x00020 to 0x7FFF
6. Read each memory location from 0x00000 to 0x7FFF and verify it contains its address
7. Write 1s complement of each cell’s memory address, into each RAM location (same addr range)
6. Read each memory location and verify it contains the 1s complement of its address
bit can only be set if the TEST input pin is high and if register bit 15 is already asserted. This bit is
automatically cleared upon test completion. Register bits 9-8 indicate pass / fail test result.
automatically cleared when RBSTRT bit 10 is set.
automatically cleared when RBSTRT bit 10 is set. When BIST failure occurs, a clue to the failing RAM
address can be read at register address 0x001E. For speed, the RAM BIST concurrently tests 4
quadrants of the RAM address range, in parallel. If test failure occurs, register address 0x001E
contains the RAM address being tested in the lowest RAM quadrant. Actual failure will occur in any of
these four locations: at RAM address “ADDR” stored in register 0x001E, or ADDR+0x2000, or
ADDR+0x4000 or ADDR+0x6000.
LBALOG bit is low, digital loopback is selected and no data is transmitted onto the selected external
MIL-STD-1553 bus. When the LBALOG bit is high, analog loopback is selected and a test word is
HOLT INTEGRATED CIRCUITS
a. Read and verify 0x0000
b. Write then read and verify 0x5555
c.
d. Write then read and verify 0x3333
e. Write then read and verify 0xCCCC
f.
g. Write then read and verify 0xF0F0
h. Write then read and verify 0x00FF
I.
j.
a. Read and verify 0xFFFF
b. Write then read and verify 0x5555
c. Write then read and verify 0xAAAA
d. Write then read and verify 0x3333
e. Write then read and verify 0xCCCC
f.
g. Write then read and verify 0xF0F0
h. Write then read and verify 0x00FF
I.
j.
Write then read and verify 0x0F0F
Write then read and verify 0xFF00
Write 0xFFFFthen increment RAM address and go to step (a)
Write then read and verify 0xAAAA
Write then read and verify 0x0F0F
Write then read and verify 0xFF00
Write 0x0000 then increment RAM address and go to step (a)
HI-6120, HI-6121
25