HI-6121PQMF HOLTIC [Holt Integrated Circuits], HI-6121PQMF Datasheet - Page 71

• Manufacturer Part Number: HI-6121PQMF
• Description: MIL-STD-1553 Remote Terminal ICs
• Manufacturer: HOLTIC [Holt Integrated Circuits]

RESET AND INITIALIZATION, Cont.
Notes:
1. After Master Reset, bits 15, 14 and 2 in the BIT Word Register depend on input pin settings. See register description. If the
MTSTOFF input pin is low, register bit 3 (BMTF) depends on memory test outcome. The remaining bits are unconditionally
reset. However if auto-initialization is enabled and EEPROM load failure occurs during the subsequent initialization process,
register bit 1 (EELF) will be set.
2. Upon SRST reset, the DBAC, DPB, MKBUSY and BCAST bits are reset for each of the 128 Control Words in the primary
Descriptor Table which starts at address 0x0200. If secondary Descriptor Tables are used (above address 0x0400), the host
must perform any necessary table reconfiguration after SRST reset.
0x000B-0x000E
0x0020-0x001F
0x0020-0x003F
0x0040-0x005F
0x0060-0x00FF
0x0100-0x01FF
0x0200-0x03FF
0x0400-0x7FFF
Address
Address
0x000A
0x0000
0x0001
0x0002
0x0003
0x0004
0x0005
0x0006
0x0007
0x0008
0x0009
0x000F
0x0010
0x0012
0x0013
0x0014
0x0015
0x0016
0x0017
0x0018
0x0019
0x0011
Hex
Hex
FIGURE 19. Summary of Changes Due to
Device Register
Configuration Register 1
Configuration Register 2
Operational Status Register
Current Command Register
Current Control Word Address Register
Descriptor Table Base Address Register
Pending Interrupt Register
1553 Status Word Bits Register
Time-Tag Register
Interrupt Log Address Register
Current Message Information Word Register
Reserved
Memory Address Pointer (HI-6121 Only)
Interrupt Enable Register
Time-Tag Utility Register
Bus A Select Register
Bus B Select Register
Built-In Test (BIT) Word Register
Alternate BIT Word Register
Test Control Register
BIST Control Register
Loopback Test Transmit Data Register
Loopback Test Receive Data Register
Reserved
RAM Structure
Temporary Receive Data Buffer, 32 Words
Interrupt Log Buffer, 32 Words
Unallocated RAM, 160 Words
Illegalization Table, 256 Words
Descriptor Table (Primary), 512 Words
Host-Assigned Data Buffers
Secondary Descriptor Tables, if used
Terminal Function
Hardware Bus Decoders
Hardware Encoders and Transmitters
Command Processing & ACTIVE Output
Terminal Status (incl ME & BCR bits)
Prior Bus Shutdown by Mode Cmd MC4 or MC20
Prior Terminal Flag Inhibit by Mode Cmd MC6
READY Output
INTMES INTHW
&
HOLT INTEGRATED CIRCUITS
Interrupt Outputs
HI-6120, HI-6121
71
MR
Master Reset or SRST Software Reset
bits 7:0 reset to 0x00
bits 15:8 match pins
Contents After
negated (high)
Contents After
See Note 1
overridden
overridden
State After
all 0x0000
all 0x0000
all 0x0000
all 0x0000
all 0x0000
all 0x0000
all 0x0000
MR
MR
MR
0x0000
0x0000
0x0000
0x0000
0x0200
0x0000
0x0000
0x0000
0x0040
0x0000
0x0000
0x0000
0x0007
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
reset
reset
reset
reset
reset
Reset
Reset
Reset
Contents After
negated (high)
Contents After
SRST Reset
SRST Reset
SRST Reset
See Note 2
no change
overridden
overridden
no change
no change
no change
no change
no change
no change
no change
no change
no change
no change
no change
no change
no change
no change
no change
no change
no change
no change
no change
no change
no change
State After
0x0200
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
reset
reset
reset
reset
set