HI-6121PQMF HOLTIC [Holt Integrated Circuits], HI-6121PQMF Datasheet - Page 14

• Manufacturer Part Number: HI-6121PQMF
• Description: MIL-STD-1553 Remote Terminal ICs
• Manufacturer: HOLTIC [Holt Integrated Circuits]

REGISTERS, Cont.
5
4
OPERATIONAL STATUS REGISTER
All sixteen register bits are active high.
pins RTA4 through RTA0, RTAP, LOCK and AUTOEN; register bits 7 - 3 are reset to logic 0 state. Register bits 8 - 0 are always
read-only. If the register’s LOCK bit is logic 0, bits 15 - 9 are read-write but cannot be written unless STEX in Configuration
Register 1 is low.
MR
Bit No.
15-11
10
9
8
7
6
MSB
-0
master reset assertion with the LOCK input pin at logic 0 state. This register is not affected by SRST software reset.
15 14 13 12 11 10 9
MCOPT0
——
AUTOEN
Mnemonic Function
RTA4 - 0
RTAP
LOCK
READY
ACTIVE
If the register LOCK bit is logic 1, bits 15 - 9 are is read-only. Once the LOCK bit is set, unlock requires a new
Mode Code Option 0.
register before status word transmission begins. If the MCOPT1 bit is logic 1, the external host
assumes responsibility for resetting the Service Request bit in the Status Word Bits register.
If this bit is logic 0, reception of a “reset remote terminal” mode command (MC8) causes automatic
assertion of SRESET software reset. If non-broadcast mode command, reset occurs after status
word transmission is complete. If this bit is logic 1, the external host assumes responsibility for
actions needed to perform terminal reset.
Not used.
Remote Terminal Address bits 4 - 0.
Remote Terminal Address Parity.
T
input signal,
bit is high, these bits are read-only. When the register LOCK bit is low
Register 1 equals 0)
terminal address and parity.
Terminal Address Lock.
After a rising edge on the
When the LOCK bit is high, this bit is read-only. When LOCK is low (and STEX in Configuration
Register 1 equals 0)
active terminal address.
Auto-Initialize Enable.
This read-only bit reflects the state of the AUTOEN input pin that applied at the rising edge on the
master reset input signal. If the register AUTOEN bit is high, device auto-initialization was performed
following
STEX bit in Configuration Register 1 to enable terminal operation. Auto-initialization of the Control
Register can optionally set STEX to begin terminal operation without host assistance. See section
entitled “Reset and Initialization” for details.
Ready status.
This read-only bit reflects the state of the output pin READY and is cleared on reset. The bit is
asserted after post-reset internal terminal initialization is complete, indicating that shared RAM is
ready to accept configuration data from the host.
Active status.
When set, this read-only bit indicates the terminal is presently processing a message. This bit reflects
the state of output pin ACTIVE and is cleared on reset. Note: Ths bit and the corresponding output pin
are asserted upon valid command detection and negated when command processing is completed.
hese bits contain the active remote terminal address. fter a rising edge on the
8
7
MR
6
these bits reflect the state of the RTA4 - 0 and RTAP
reset. When auto-initialization is complete, the device waits for the host to assert the
5
After rising edge on the
4
HOLT INTEGRATED CIRCUITS
3
auto-initialization (see bit 8) or the host can overwrite these bits to change the
auto-initialization (see bit 8) or the host can write
(0x0002)
2
MR
HI-6120, HI-6121
1
master reset input signal,
0
LSB
14
MR
master reset input pin, bits 15 - 8 reflect the state of input
this bit reflects the state of the LOCK input pin.
A
input pins. When
(and STEX in Configuration
this bit to logic 1 to lock the
the register LOCK
MR
master reset
MR