HI-6121PQMF HOLTIC [Holt Integrated Circuits], HI-6121PQMF Datasheet - Page 23

• Manufacturer Part Number: HI-6121PQMF
• Description: MIL-STD-1553 Remote Terminal ICs
• Manufacturer: HOLTIC [Holt Integrated Circuits]

REGISTERS, Cont.
BUILT-IN TEST WORD REGISTER
Bits 4-11 in this 16-bit register are read-write, the remaining bits are read-only. The ten assigned bits are written by the device
when predetermined events occur. The host may overwrite the device-written bits 5 and 4. After
12, 5-4 and 0 are reset. Bits 15-14 will be set if the corresponding TXINHA or TXINHB input pins are high. Bits 3-1 will be set if
RT address parity error, or post-
software reset.
If the ALTBITW option bit in Configuration Register 2 is zero when a valid “transmit BIT word” mode command (MC19) is
received, the current value in this register is transmitted as the mode data word in the terminal response. The value is also
copied to the assigned data buffer for MC19, after mode command fulfillment.
Bit No.
15
14
13
12
11-6
5
4
3
2
1
0
MSB
15 14 13 12 11 10 9
Mnemonic Interrupt Type
TXASD
TXBSD
RXASD
RXBSD
——
BLBFA
BLBFB
BMTF
RTAPF
EELF
TFBINH
ARE USER DEFINED
UNASSIGNED BITS
Transmitter A Shut Down.
Transmitter B Shut Down.
These read-only bits are set when the corresponding bus transmitter was disabled by assertion of the
bus TXINHA or TXINHB input pin, or by fulfillment of a “transmitter shutdown” mode command MC4
or MC20. Refer to the description for the SDSEL bit in Configuration Register 1 and the description for
the MCOPT4 bit in Configuration Register 2 for further information.
Receiver A Shut Down.
Receiver B Shut Down.
These read-only bits are set when the corresponding bus receiver was disabled concurrently with the
bus transmitter by a “transmitter shutdown” mode command MC4 or MC20. Refer to the description
for the SDSEL bit in Configuration Register 1 and the description for the MCOPT4 bit in Configuration
Register 2 for further information.
User assigned bits.
BIST Loopback Fail Bus A.
This bit is set if Bus A loopback failure error occurs during built-in self-test.
BIST Loopback Fail Bus B.
This bit is set if Bus B loopback failure error occurs during built-in self-test.
BIST Memory Test Fail.
This bit is set if error occurs during built-in self-test for device RAM memory.
RTAddress Parity Failure.
This bit is asserted when Operational Status Register bits 15:10 reflect parity error. After
reset, bits 15:10 in the Operational Status Register reflect input pin states, but will be overwritten if
subsequent auto-initialization is performed (if AUTOEN pin is high) and the initialization EEPROM
contains different data for Operational Status Register bits 15:10.
Auto-Initialization EEPROM Load Fail.
This bit only applies when auto-initialization is enabled (AUTOEN input pin state equals 1). This bit is
set if, after
When this occurs, bit 0 or bit 1 will be set in the Operational Status Register (0x0002) to indicate type
of failure.
Terminal Flag Bit Inhibited.
This bit is set when the Terminal Flag status bit is disabled while fulfilling an “inhibit terminal flag bit”
mode code command (MC6). This bit is reset if terminal flag status bit disablement is later cancelled
by an “override inhibit terminal flag bit” mode code command (MC7).
8
7
MR
6
MR
memory test or auto-initialization failure occurred. This register is cleared by SRST
5
master reset, failure occurs when copying serial EEPROM to registers and RAM.
4
HOLT INTEGRATED CIRCUITS
(0x0014)
3
2
HI-6120, HI-6121
1
0
LSB
23
MR
pin master reset, bits 13-
MR
master