HD6417708SF60V Renesas Electronics America, HD6417708SF60V Datasheet - Page 104

• Manufacturer Part Number: HD6417708SF60V
• Description: IC SUPERH MPU ROMLESS 208LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417708SF60V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 60MHz
• Connectivity: EBI/EMI, SCI, SmartCard
• Peripherals: POR, WDT
• Number Of I /o: 8
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -

Table 4.2
Exception
Type
General
interrupt
requests
Notes: 1. Priorities are indicated from high to low, 1 being highest and 4 being lowest.
4.2.3
Processor resets and interrupts are asynchronous events unrelated to the instruction stream. All
exception events are prioritized to establish an acceptance order whenever two or more exception
events occur simultaneously. The power-on reset and manual reset may not occur simultaneously,
so they have the same priority.
All general exception events occur in a relative order in the execution sequence of an instruction
(i.e., execution order), but are handled at priority level 2 in instruction-stream order (i.e., program
order), where an exception detected in a preceding instruction is accepted prior to an exception
detected in a subsequent instruction.
Three general exception events (reserved instruction code exception, unconditional trap, and
illegal slot instruction exception) are detected in the decode stage of different instructions and are
mutually exclusive events in the instruction pipeline. They have the same execution priority.
Figure 4.2 shows the order of general exception acceptance.
84
2. The user defines the break point traps. 1 is a break point before instruction execution
3. Use software to specify relative priorities of external hardware interrupts and peripheral
Acceptance of Exceptions
and 11 is a break point after instruction execution. For an operand break point, use 11.
module interrupts (see section 6, Interrupt Controller (INTC)).
Current
Instruction Exception Event
Completed
Vectored Exception Events (cont)
Nonmaskable
interrupt
External hardware
interrupt
Peripheral module
interrupt
Priority*
3
4*
4*
3
3
1
Exception
Order
—
—
—
Vector
Address
—
—
—
Vector
Offset
H'00000600
H'00000600
H'00000600