HD6417708SF60V Renesas Electronics America, HD6417708SF60V Datasheet - Page 316

• Manufacturer Part Number: HD6417708SF60V
• Description: IC SUPERH MPU ROMLESS 208LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417708SF60V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 60MHz
• Connectivity: EBI/EMI, SCI, SmartCard
• Peripherals: POR, WDT
• Number Of I /o: 8
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -

10.3.10 Bus Arbitration
When a bus release request (BREQ) is received from an external device, buses are released after
the bus cycle being executed is completed and a bus grant signal (BACK) is output. The bus is not
released during burst transfers for cache fills. In the case of multiple bus cycles generated because
the data bus width is smaller than the access size—for example, in longword access to 8-bit-wide
memory—bus arbitration is not performed between bus cycles. At the negation of BREQ, BACK
is negated and bus use is restarted. See Appendix B, Pin States, for the pin status when the bus is
released.
The SH7708 Series sometimes needs to retrieve a bus it has released. For example, when memory
generates a refresh request or an interrupt request internally, the SH7708 Series must perform the
appropriate processing. The SH7708 Series has a bus request signal (IRQOUT) for this purpose.
When it must retrieve the bus, it asserts the IRQOUT signal. Devices asserting an external bus
release request receive the assertion of the IRQOUT signal and negate the BREQ signal to release
the bus. The SH7708 Series retrieves the bus and carries out the processing.
296
CKIO
A25 to A0
CSm
CSn
BS
RD/WR
RD
D31 to D0
Area m inter-access wait specification
Area m read
T1
Figure 10.50 Waits between Access Cycles
T2
Twait
Area n space read
T1
Area n inter-access wait specification
T2
Twait
Area n space write
T1
T2