HD6417708SF60V Renesas Electronics America, HD6417708SF60V Datasheet - Page 277

IC SUPERH MPU ROMLESS 208LQFP

HD6417708SF60V

Manufacturer Part Number
HD6417708SF60V
Description
IC SUPERH MPU ROMLESS 208LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet

Specifications of HD6417708SF60V

Core Processor
SH-2
Core Size
32-Bit
Speed
60MHz
Connectivity
EBI/EMI, SCI, SmartCard
Peripherals
POR, WDT
Number Of I /o
8
Program Memory Type
ROMless
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
208-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Ram Size
-
Program Memory Size
-
Data Converters
-

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417708SF60V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD6417708SF60V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
Address Multiplexing: Synchronous DRAM can be connected without external multiplexing
circuitry in accordance with the address multiplex specification bits AMX1 and AMX0 in MCR.
Table 10.13 shows the relationship between the address multiplex specification bits and the bits
output at the address pins.
A25–A16 and A0 are not multiplexed; the original values are always output at these pins.
When A0, the LSB of the synchronous DRAM address, is connected to the SH7708 Series, it
performs longword address specification. Connection should therefore be made in this order:
connect pin A0 of the synchronous DRAM to pin A2 of the SH7708 Series, then connect pin A1
to pin A3. Table 10.14 shows the example of correspondence between SH7708 Series and
synchronous DRAM address pins.
Table 10.13 Relationship between SZ, AMX, and Address Multiplex Output
AMX1 AMX0 Output Timing
0
0
1
1
Notes: 1. L/H is a bit used in the command specification; it is fixed at L or H according to the
Setting
2. Bank address specification.
0
1
0
1
access mode.
Column address
Row address
Column address
Row address
Column address
Row address
Column address
Row address
A1 to A8
A1 to A8
A9 to A16
A1 to A8
A10 to A17 A18
A1 to A8
A11 to A18 A19
A1 to A8
A9 to A16
A9
A9
A17
A9
A9
A9
A17
External Address Pins
A10
A10
A18
A10
A19
A10
A20
L/H*
A18
1
A11
A11
A19
A11
A20
A11
A21
A19*
A19*
2
2
A12
L/H*
A20
L/H*
A21
L/H*
A22
A12
A20
1
1
1
A21*
A21*
A22*
A22*
A23*
A23*
A13
A21
A13
2
2
2
2
2
2
A14
A14
A22
A14
A23
A14
A24
A14
A22
A15
A15
A23
A15
A24
A15
A25
A15
A23
257

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