HD6417708SF60V Renesas Electronics America, HD6417708SF60V Datasheet - Page 40

IC SUPERH MPU ROMLESS 208LQFP

HD6417708SF60V

Manufacturer Part Number
HD6417708SF60V
Description
IC SUPERH MPU ROMLESS 208LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet

Specifications of HD6417708SF60V

Core Processor
SH-2
Core Size
32-Bit
Speed
60MHz
Connectivity
EBI/EMI, SCI, SmartCard
Peripherals
POR, WDT
Number Of I /o
8
Program Memory Type
ROMless
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
208-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Ram Size
-
Program Memory Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417708SF60V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD6417708SF60V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
2.3
2.3.1
Data Length: The SH7708 Series instruction set is implemented with fixed-length 16-bit wide
instructions executed in a pipelined sequence with single-cycle execution for most instructions.
All operations are executed in 32-bit longword units. Memory can be accessed in 8-bit byte, 16-bit
word, or 32-bit longword units, with byte or word units sign-extended into 32-bit longwords.
Literals are sign-extended in arithmetic operations (MOV, ADD, and CMP/EQ instructions) and
zero-extended in logical operations (TST, AND, OR, and XOR instructions).
Load/Store Architecture: The SH7708 Series features a load-store architecture in which basic
operations are executed in registers. Operations requiring memory access are executed in registers
following register loading, except for bit-manipulation operations such as logical AND functions,
which are executed directly in memory.
Delayed Branching: Unconditional branching is implemented as delayed branch operations.
Pipeline disruptions due to branching are minimized by the execution of the instruction following
the delayed branch instruction prior to branching. Conditional branch instructions are of two
kinds, delayed and normal.
20
BRA
ADD
Address A + 4
Address A + 8
Address A
Instruction Features
Execution Environment
TRGET
R1, R0
Address A
Byte0 Byte1 Byte2 Byte3
31
Address A + 1 Address A + 3
Figure 2.7 Byte, Word, and Longword Alignment
Word0
Big-endian mode
23
;ADD is executed prior to branching to TRGET
Longword
Address A + 2
15
Word1
7
Address A + 11
0
Byte3 Byte2 Byte1 Byte0
31
Address A + 10 Address A + 8
Word1
Little-endian mode
23
Longword
Address A + 9
15
Word0
7
0
Address A + 8
Address A + 4
Address A

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