HD6417708SF60V Renesas Electronics America, HD6417708SF60V Datasheet - Page 83
HD6417708SF60V
Manufacturer Part Number
HD6417708SF60V
Description
IC SUPERH MPU ROMLESS 208LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.HD6417708SF60V.pdf
(635 pages)
Specifications of HD6417708SF60V
Core Processor
SH-2
Core Size
32-Bit
Speed
60MHz
Connectivity
EBI/EMI, SCI, SmartCard
Peripherals
POR, WDT
Number Of I /o
8
Program Memory Type
ROMless
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
208-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Ram Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6417708SF60V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD6417708SF60V
Manufacturer:
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Quantity:
20 000
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3.3.3
The results of address comparison determine whether a specific virtual page number is registered
in the TLB. The virtual page number of the virtual address that accesses external memory is
compared to the virtual page number of the indexed TLB entry. The ASID within the PTEH is
compared to the ASID of the indexed TLB entry. All four ways are searched simultaneously. If the
compared values match, and the indexed TLB entry is valid (V bit = 1), the hit is registered.
It is necessary to have the software ensure that TLB hits do not occur simultaneously in more than
one way, as hardware operation is not guaranteed if this happens. For example, if there are two
identical TLB entries with the same VPN and a setting is made such that a TLB hit is made only
by a process with ASID = H'FF when one is in the shared state (SH = 1) and the other in the non-
shared state (SH = 0), then if the ASID in PHE is set to H'FF, there is a possibility of simultaneous
TLB hits in both these ways. It is therefore necessary to ensure that this kind of setting is not made
by the software.
The object compared varies depending on the page management information (SZ, SH) in the TLB
entry. It also varies depending on whether the system supports multiple virtual memory or single
virtual memory.
The page size information determines whether VPN (11–10) is compared. VPN (11–10) is
compared for 1-kbyte pages (SZ = 0) but not for 4-kbyte pages (SZ = 1).
31
0
Virtual address
31
VPN(31–17)
TLB Address Comparison
Index
VPN(11–10)
17
Address array
16
Figure 3.7 TLB Indexing (IX = 0)
12
11
ASID(7–0)
0
V
Way 0–3
PPN(31–10) PR(1–0) SZ C
Data array
D SH
63
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