HD6417708SF60V Renesas Electronics America, HD6417708SF60V Datasheet - Page 156

• Manufacturer Part Number: HD6417708SF60V
• Description: IC SUPERH MPU ROMLESS 208LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417708SF60V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 60MHz
• Connectivity: EBI/EMI, SCI, SmartCard
• Peripherals: POR, WDT
• Number Of I /o: 8
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -

7.3.3
1. In the case of a data access cycle break, the bits used for comparison with the address bus
2. When data value is included in break condition in channel B
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depend on the break bus cycle register (BBRA/BBRB) operand size specification, as follows:
Operand size
Not included in conditions (00):
Byte (01):
Word (10):
Longword (11):
When the data value is included in the break conditions, set the DBEB bit in the break control
register (BRCR) to 1. In this case, break data register B (BDRB) and break data mask register
B (BDMRB) settings are needed in addition to the address condition. A user break trap is
generated on a match of the address condition and the data condition.
Bits IDB1 and IDB0 of break bus cycle register B (BBRB) should be set to 00 or 01.
When byte data is specified, set the same data in the two bytes comprising bits 15–8 and bits
7–0 in break data register B (BDRB) and break mask register B (BDMRB). If word or byte is
designated, bits 31–16 of BDRB and BDMRB are ignored.
Data Access Cycle Break
Compared address
For byte address, comparison with address bits A31–A0
For word address, comparison with address bits A31–A1
For longword address, comparison with address bits
A31–A2
Comparison with address bits A31–A0
Comparison with address bits A31–A1
Comparison with address bits A31–A2