HD6417708SF60V Renesas Electronics America, HD6417708SF60V Datasheet - Page 225

• Manufacturer Part Number: HD6417708SF60V
• Description: IC SUPERH MPU ROMLESS 208LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417708SF60V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 60MHz
• Connectivity: EBI/EMI, SCI, SmartCard
• Peripherals: POR, WDT
• Number Of I /o: 8
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -

Note: * SH7708R A-mask version only
Bits 15 and 14 —Reserved: These bits always read 0. The write value should always be 0.
Bit 15—WAIT Signal Sampling Timing Specification (WAITSEL) [A-mask version only]
Bit 15: WAITSEL
0
1
Bits 2n + 1, 2n—Area n (6–0) Intercycle Idle Specification (AnIW1, AnIW0): These bits specify
the number of idles inserted between bus cycles when switching between physical space area n (6–
0) to another space or between a read access to a write access in the same physical space.
Bit 2n + 1: AnIW1
0
1
Initial value:
Initial value:
Bit name: WAITSEL*
Bit name:
R/W:
R/W:
Bit:
Bit:
A3IW1
Bit 2n: AnIW0
0
1
0
1
R/W
Description
WAIT signal is sampled at rise of CKIO
In this case, the WAIT signal should be input synchronously
WAIT signal is sampled at fall of CKIO
In this case, the WAIT signal can be input asynchronously
15
W
0
7
1
A3IW0
R/W
14
—
0
R
6
1
A6IW1
A2IW1
R/W
R/W
Description
No idle cycles
1 idle cycle inserted
2 idle cycles inserted
3 idle cycles inserted
13
1
5
1
A6IW0
A2IW0
R/W
R/W
12
1
4
1
A5IW1
A1IW1
R/W
R/W
11
1
3
1
A5IW0
A1IW0
R/W
R/W
10
1
2
1
A4IW1
A0IW1
R/W
R/W
9
1
1
1
(Initial value)
(Initial value)
A4IW0
A0IW0
R/W
R/W
8
1
0
1
205