HD6417708SF60V Renesas Electronics America, HD6417708SF60V Datasheet - Page 180

• Manufacturer Part Number: HD6417708SF60V
• Description: IC SUPERH MPU ROMLESS 208LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417708SF60V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 60MHz
• Connectivity: EBI/EMI, SCI, SmartCard
• Peripherals: POR, WDT
• Number Of I /o: 8
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -

3. Crystal Oscillator: This oscillator is used when a crystal oscillator element is connected to the
4. Divider 1: Divider 1 generates a clock at the operating frequency used by the internal clock.
5. Divider 2: Divider 2 generates a clock at the operating frequency used by the peripheral clock.
6. Clock Frequency Control Circuit: The clock frequency control circuit controls the clock
7. Standby Control Circuit: The standby control circuit controls the status of the clock pulse
8. Frequency Control Register: The frequency control register has control bits assigned for the
9. Standby Control Register: The standby control register has bits for controlling the power-down
Note: * SH7708R only
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XTAL and EXTAL pins. It operates according to the clock operating mode setting.
The operating frequency can be 1, 1/2, 1/3*, or 1/4 times the output frequency of PLL circuit 1,
as long as it stays at or above the clock frequency of the CKIO pin. The division ratio is set in
the frequency control register.
The operating frequencies can be 1, 1/2, 1/3*, or 1/4 times the output frequency of PLL Circuit
1 or the clock frequency of the CKIO pin, as long as it stays at or below the clock frequency of
the CKIO pin. The division ratio is set in the frequency control register.
frequency using the MD pin and the frequency control register.
generator and other modules during clock switching and sleep/standby modes.
following functions: clock output/non-output from the CKIO pin, on/off control of PLL circuit
1, PLL standby, the frequency multiplication ratio of PLL 1, and the frequency division ratio
of the internal clock and the peripheral clock.
modes. See section 8, Power-Down Modes, for more information.