HD6417708SF60V Renesas Electronics America, HD6417708SF60V Datasheet - Page 112

• Manufacturer Part Number: HD6417708SF60V
• Description: IC SUPERH MPU ROMLESS 208LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417708SF60V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 60MHz
• Connectivity: EBI/EMI, SCI, SmartCard
• Peripherals: POR, WDT
• Number Of I /o: 8
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -

92
TLB protection exception
The PC and SR of the instruction that generated the exception are saved to the SPC and SSR,
respectively. If the exception occurred during a read, H'0A0 is set in EXPEVT; if the exception
occurred during a write, H'0C0 is set in EXPEVT. The BL, MD, and RB bits in SR are set to 1
and a branch occurs to PC = VBR + H'0100.
Address error
a. Instruction fetch from odd address (4n + 1, 4n + 3)
b. Word data accessed from addresses other than word boundaries (4n + 1, 4n + 3)
c. Longword accessed from addresses other than longword boundaries (4n + 1, 4n + 2,
d. Virtual space accessed in user mode in the area H'80000000 to H'FFFFFFFF.
Unconditional trap
Conditions: When a hit access violates the TLB protection information (PR bits) shown
Operations: The virtual address (32 bits) that caused the exception is set in TEA and the
Conditions:
Operations: The virtual address (32 bits) that caused the exception is set in TEA. The PC
Conditions: TRAPA instruction executed
Operations: The exception is a processing-completion type, so the PC of the instruction
below:
corresponding virtual page number (22 bits) is set in PTEH (31–10). The ASID of PTEH
indicates the ASID at the time the exception occurred. The way that generated the
exception is set in the RC bits in MMUCR.
4n + 3)
and SR of the instruction that generated the exception are saved to the SPC and SSR,
respectively. If the exception occurred during a read, H'0E0 is set in EXPEVT; if the
exception occurred during a write, H'100 is set in EXPEVT. The BL, MD, and RB bits in
SR are set to 1 and a branch occurs to PC = VBR + H'0100.
For details see section 3.5.5, Processing Flow in Event of MMU Exception.
after the TRAPA instruction is saved to the SPC. SR from the time when the TRAPA
instruction was executing is saved to SSR. The 8-bit immediate value in the TRAPA
instruction is quadrupled and set in TRA(9–0). H'160 is set in EXPEVT. The BL, MD, and
RB bits in SR are set to 1 and a branch occurs to PC = VBR + H'0100.
PR
00
01
10
11
Privileged mode
Only read enabled
Read/write enabled
Only read enabled
Read/write enabled
User mode
No access
No access
Only read enabled
Read/write enabled