HD6417708SF60V Renesas Electronics America, HD6417708SF60V Datasheet - Page 222

• Manufacturer Part Number: HD6417708SF60V
• Description: IC SUPERH MPU ROMLESS 208LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417708SF60V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 60MHz
• Connectivity: EBI/EMI, SCI, SmartCard
• Peripherals: POR, WDT
• Number Of I /o: 8
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -

Bits 6 and 5—Area 6 Burst Enable (A6BST1, A6BST0): These bits specify whether to use burst
ROM and PCMCIA burst mode in physical space area 6. When burst ROM and PCMCIA burst
mode are used, they set the number of burst transfers.
Bit 6: A6BST1
0
1
Bits 4 to 2—Area 2, Area 3 Memory Type (DRAMTP2, DRAMTP1, DRAMTP0): These bits
designate the types of memory connected to physical space areas 2 and 3. Normal memory, such
as ROM, SRAM, or flash RAM, can be directly connected. Pseudo-SRAM, DRAM, and
synchronous DRAM can also be directly connected.
Bit 4: DRAMTP2 Bit 3: DRAMTP1 Bit 2: DRAMTP0 Description
0
1
Note: * When selecting these bits, set the area 2 and 3 bus widths as word. The MD5 pin output is
Bit 1—Area 5 Bus Type (A5PCM): Designates whether to access physical space area 5 as
PCMCIA space.
Bit 1: A5PCM
0
1
Note: * MD3 pin output is CE2A.
202
the RAS2 signal.
0
1
0
1
Bit 5: A6BST0
0
1
0
1
Description
Access physical space area 5 as normal memory.
Access physical space area 5 as PCMCIA space.*
0
1
0
1
0
1
0
1
Description
Access area 6 as normal memory.
Burst access of area 6 (4 consecutive accesses). Can
be used when bus width is 8, 16, or 32.
Burst access of area 6 (8 consecutive accesses). Can
be used only when bus width is 8 or 16.
Burst access of area 6 (16 consecutive accesses). Can
be used only when bus width is 8.
Areas 2 and 3 are normal memory
Area 2: normal memory; area 3: PSRAM
Area 2: normal memory; area 3: SDRAM
Areas 2 and 3 are SDRAM
Area 2: normal memory; area 3: DRAM
Areas 2 and 3 are DRAM *
Reserved (cannot be set)
Reserved (cannot be set)
(Initial value)
(Initial value)
(Initial value)