HD6417708SF60V Renesas Electronics America, HD6417708SF60V Datasheet - Page 234

• Manufacturer Part Number: HD6417708SF60V
• Description: IC SUPERH MPU ROMLESS 208LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417708SF60V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 60MHz
• Connectivity: EBI/EMI, SCI, SmartCard
• Peripherals: POR, WDT
• Number Of I /o: 8
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -

10.2.6
The DRAM area control register (DCR) is a 16-bit read/write register that specifies RAS and CAS
timing and burst control for DRAM connected to area 2. It also specifies address multiplexing and
controls refreshing. When DRAM is connected to area 2, the bus width is fixed at 16 bits. In such
cases, set the area 3 bus width to 16 bits as well. Other areas should be 8 bits or 16 bits. DCR is
initialized to H'0000 by a power-on reset, but is not initialized by a manual resets or in standby
mode. Do not access external memory outside area 2 until initialization of this register is
complete.
Bits 15 and 14—RAS Precharge Time (TPC1, TPC0): These bits set the RAS precharge time for
the DRAM connected to area 2.
Bit 15: TPC1
0
1
Bits 13 and 12—RAS–CAS Delay (RCD1, RCD0): These bits set the RAS–CAS delay time for
the DRAM connected to area 2.
Bit 13: RCD1
0
1
214
Initial value:
Initial value:
Bit name:
Bit name:
DRAM Control Register (DCR)
R/W:
R/W:
Bit:
Bit:
Bit 14: TPC0
0
1
0
1
Bit 12: RCD0
0
1
0
1
TPC1
R/W
15
—
0
7
0
R
TPC0
R/W
R/W
BE
14
0
6
0
Normally
1 cycle (Initial value)
2 cycles
3 cycles
4 cycles
Description
1 cycle
2 cycles
3 cycles
4 cycles
RCD1
R/W
13
—
0
5
0
R
AMX1
RCD0
R/W
R/W
12
0
4
0
AMX0
Description
R/W
Immediately after Self-Refresh
2 cycles (Initial value)
5 cycles
8 cycles
11 cycles
11
—
0
R
3
0
RFSH
R/W
10
—
0
R
2
0
RMODE
TRAS1
R/W
R/W
9
0
1
0
(Initial value)
TRAS0
R/W
—
8
0
0
0
R