HD6417708SF60V Renesas Electronics America, HD6417708SF60V Datasheet - Page 188

• Manufacturer Part Number: HD6417708SF60V
• Description: IC SUPERH MPU ROMLESS 208LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417708SF60V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 60MHz
• Connectivity: EBI/EMI, SCI, SmartCard
• Peripherals: POR, WDT
• Number Of I /o: 8
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -

Table 9.5
Clock
Mode
7
Notes: 1. Input clock frequency is 1
Cautions:
1. When clock operating modes 3 and 4 are used:
2. The input to divider 1 becomes the output of:
3. The input of divider 2 becomes the output of:
4. The frequency of the internal clock (I ) becomes:
168
2. Max frequency : I = 100 MHz, B = (CKIO) = 60 MHz, P = 30 MHz
FRQCR
H'0100
H'0101
H'0102
H'0111
H'0112
H'0115
H'0116
H'0122
H'0126
H'012A
H’A100
H’E100
H’E101
The on/off state of PLL circuit 1 is set by the frequency control register.
PLL circuit 1 is initialized to the off state by a power-on reset.
Always turn PLL circuit 1 off before going into standby mode.
PLL circuit 1 when PLL circuit 1 is on.
PLL circuit 2 when PLL circuit 1 is off and PLL circuit 2 is on.
Divider 3 when PLL circuit 1 is off and PLL circuit 2 is off.
PLL circuit 1 when the clock operating mode is 0–2 or 7.
PLL circuit 2 when the clock operating mode is 3 and 4 and PLL circuit 2 is on.
Divider 3 when the clock operating mode is 3 and 4 and PLL circuit 2 is off.
The product of the frequency of the CKIO pin, the frequency multiplication ratio of
PLL circuit 1, and the division ratio of divider 1 when PLL circuit 1 is on.
Equal to the frequency of CKIO pin when PLL circuit 1 is off.
Range of Usable Frequencies for Each Clock Operating Mode(SH7708R) (cont)
PLL1
ON ( 1)
ON ( 1)
ON ( 1)
ON ( 2)
ON ( 2)
ON ( 2)
ON ( 2)
ON ( 4)
ON ( 4)
ON ( 4)
ON ( 3))
ON ( 3)
ON ( 3)
PLL2
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
Clock
Rate*
(I:B:P)
1:1:1
1:1:1/2
1:1:1/4
2:1:1
2:1:1/2
1:1:1
1:1:1/2
4:1:1
2:1:1
1:1:1
3:1:1
1:1:1
1:1:1/2
1
Input Frequency
Range
16 MHz to 33.3 MHz
16 MHz to 60 MHz
16 MHz to 60 MHz
16 MHz to 33.3 MHz
16 MHz to 50 MHz
16 MHz to 33.3 MHz
16 MHz to 50 MHz
16 MHz to 25 MHz
16 MHz to 25 MHz
16 MHz to 25 MHz
25 MHz to 33.3 MHz
25 MHz to 33.3 MHz
25 MHz to 33.3 MHz
CKIO Frequency
Range
16 MHz to 33.3 MHz
16 MHz to 60 MHz
16 MHz to 60 MHz
16 MHz to 33.3 MHz
16 MHz to 50 MHz
16 MHz to 33.3 MHz
16 MHz to 50 MHz
16 MHz to 25 MHz
16 MHz to 25 MHz
16 MHz to 25 MHz
25 MHz to 33.3 MHz
25 MHz to 33.3 MHz
25 MHz to 33.3 MHz